LOW POWER IMAGING SYSTEM WITH SINGLE PHOTON AVALANCHE DIODE PHOTON COUNTERS AND GHOST IMAGE REDUCTION
    51.
    发明申请
    LOW POWER IMAGING SYSTEM WITH SINGLE PHOTON AVALANCHE DIODE PHOTON COUNTERS AND GHOST IMAGE REDUCTION 有权
    具有单光子光电二极管光子计数器和减少图像的低功率成像系统

    公开(公告)号:US20150163429A1

    公开(公告)日:2015-06-11

    申请号:US14100941

    申请日:2013-12-09

    Inventor: Tiejun Dai Rui Wang

    Abstract: An imaging system includes a pixel array including a plurality of pixels. Each one of the pixels includes a single photon avalanche diode (SPAD) coupled to detect photons in response to incident light. A photon counter included in readout circuitry coupled to each pixel to count a number of photons detected by each pixel. The photon counter is coupled to stop counting photons in each pixel when a threshold photon count is reached for each pixel. Control circuitry is coupled to the pixel array to control operation of the pixel array. The control circuitry includes an exposure time counter coupled to count a number of exposure times elapsed before each pixel detects the threshold photon count. Respective exposure time counts and photon counts are combined for each pixel of the pixel array.

    Abstract translation: 成像系统包括包括多个像素的像素阵列。 每个像素包括耦合以响应于入射光检测光子的单个光子雪崩二极管(SPAD)。 包括在耦合到每个像素的读出电路中的光子计数器以对由每个像素检测的多个光子进行计数。 当达到每个像素的阈值光子计数时,光子计数器被耦合以停止计数每个像素中的光子。 控制电路耦合到像素阵列以控制像素阵列的操作。 控制电路包括曝光时间计数器,其被耦合以对每个像素检测到阈值光子计数之前经过的曝光次数进行计数。 对像素阵列的每个像素组合相应的曝光时间计数和光子计数。

    Image Sensor Having NMOS Source Follower With P-Type Doping In Polysilicon Gate
    52.
    发明申请
    Image Sensor Having NMOS Source Follower With P-Type Doping In Polysilicon Gate 有权
    具有NMOS源的图像传感器,在多晶硅栅极中具有P型掺杂

    公开(公告)号:US20150163428A1

    公开(公告)日:2015-06-11

    申请号:US14097779

    申请日:2013-12-05

    Inventor: Tiejun Dai

    Abstract: An image sensor array has a tiling unit comprising a source follower stage coupled to buffer signals from a photodiode when the unit is read onto a sense line, the source follower stage differs from conventional sensor arrays because it uses an N-channel transistor having a P-doped polysilicon gate. In embodiments, other transistors of the array have conventional N-channel transistors with N-doped polysilicon gates.

    Abstract translation: 图像传感器阵列具有平铺单元,其包括源单元级耦合到源单元读取到感测线上时来自光电二极管的信号,源极跟随器级与常规传感器阵列不同,因为它使用具有P 掺杂多晶硅栅极。 在实施例中,阵列的其它晶体管具有具有N掺杂多晶硅栅极的常规N沟道晶体管。

    IMAGE SENSOR WITH FAST INTRA-FRAME FOCUS
    53.
    发明申请
    IMAGE SENSOR WITH FAST INTRA-FRAME FOCUS 有权
    具有快速帧内聚焦的图像传感器

    公开(公告)号:US20140340549A1

    公开(公告)日:2014-11-20

    申请号:US13950970

    申请日:2013-07-25

    CPC classification number: H04N5/335 H04N5/23212

    Abstract: A method of focusing an image sensor includes scanning a first portion of an image frame from an image sensor a first time at a first rate to produce first focus data. A second portion of the image frame from the image sensor is scanned at a second rate to read image data from the second portion. The first rate is greater than the second rate. The first portion of the image frame is scanned a second time at the first rate to produce second focus data. The first focus data and the second focus data are compared, and the focus of a lens is adjusted in response to the comparison of the first focus data and the second focus data.

    Abstract translation: 聚焦图像传感器的方法包括以第一速率首先从图像传感器扫描图像帧的第一部分以产生第一焦点数据。 以第二速率扫描来自图像传感器的图像帧的第二部分,以从第二部分读取图像数据。 第一个比率大于第二个比率。 以第一速率第二次扫描图像帧的第一部分以产生第二焦点数据。 比较第一焦点数据和第二焦点数据,并且响应于第一焦点数据和第二焦点数据的比较来调整透镜的焦点。

    ACQUIRING GLOBAL SHUTTER-TYPE VIDEO IMAGES WITH CMOS PIXEL ARRAY BY STROBING LIGHT DURING VERTICAL BLANKING PERIOD IN OTHERWISE DARK ENVIRONMENT
    54.
    发明申请
    ACQUIRING GLOBAL SHUTTER-TYPE VIDEO IMAGES WITH CMOS PIXEL ARRAY BY STROBING LIGHT DURING VERTICAL BLANKING PERIOD IN OTHERWISE DARK ENVIRONMENT 有权
    采用CMOS像素阵列获取全球快照类型的视频图像,在其他深色环境中的垂直空白期间通过光线照射

    公开(公告)号:US20140078277A1

    公开(公告)日:2014-03-20

    申请号:US13622976

    申请日:2012-09-19

    Abstract: Introduce CMOS pixel array into dark environment and acquiring video image frames. During a first frame, reset each row of pixels sequentially, and one row at a time, and then read each row of pixels sequentially, and one row at a time. During a second frame, reset each row of pixels sequentially, and one row at a time, and then read each row of pixels sequentially, and one row at a time. Control a light source to illuminate the dark environment during at least a portion of a vertical blanking period between the reading of the last row during the first frame and the reading of the first row during the second frame. Control the light source to not illuminate the dark environment: (a) between the reading the first and last rows during the first frame; and (b) between the reading the first and last rows during the second frame.

    Abstract translation: 将CMOS像素阵列引入黑暗环境并获取视频图像帧。 在第一帧期间,顺序地重置每行像素,一次重复一行,然后依次读取每行像素,并一次读取一行。 在第二帧期间,顺序地重置每行像素,并且每次重复一行,然后依次读取每行像素,并一次读取一行。 控制光源以在第一帧期间在最后一行的读取和第二帧期间的第一行的读取期间的垂直消隐周期的至少一部分期间照亮黑暗环境。 控制光源不照亮黑暗环境:(a)在第一帧读取第一行和最后一行; 和(b)在第二帧期间读取第一行和最后一行之间。

    PIXEL CIRCUIT FOR HIGH DYNAMIC RANGE IMAGE SENSOR

    公开(公告)号:US20240015414A1

    公开(公告)日:2024-01-11

    申请号:US17810966

    申请日:2022-07-06

    CPC classification number: H04N5/3559 H04N5/3591 H04N5/378 H04N5/347 H04N5/379

    Abstract: A pixel circuit includes a first photodiode and a second photodiode. The first and second photodiodes photogenerate charge in response to incident light. A first transfer transistor is coupled to the first photodiode. A first floating diffusion is coupled to the first transfer transistor. A second transfer transistor is coupled to the second photodiode. A second floating diffusion is coupled to the second transfer transistor. A dual floating diffusion transistor is coupled between the first and second floating diffusions. An overflow transistor is coupled to the second photodiode. A capacitor is coupled between a voltage source and the overflow transistor. A capacitor readout transistor is coupled between the capacitor and the second floating diffusion. An anti-blooming transistor coupled between the first photodiode and a power line.

    PIXEL DESIGNS WITH REDUCED LOFIC RESET AND SETTLING TIMES

    公开(公告)号:US20230421922A1

    公开(公告)日:2023-12-28

    申请号:US17849403

    申请日:2022-06-24

    CPC classification number: H04N5/378 H04N5/3559 H01L27/14643 H01L27/14612

    Abstract: Pixel designs with reduced LOFIC reset and settling times are disclosed herein. In one embodiment, a pixel cell includes a photosensor configured to photogenerate image charge in response to incident light, a floating diffusion to receive the image charge from the photosensor, a transfer transistor coupled between the floating diffusion and the photosensor to transfer the image charge to the floating diffusion, and a first reset transistor coupled between the floating diffusion and the voltage supply. The pixel cell further includes a capacitor having two ends, and a second reset transistor. A first end of the capacitor is coupled to the floating diffusion. The second reset transistor is coupled between a second end of the capacitor and the voltage supply.

    Voltage domain global shutter readout circuit

    公开(公告)号:US11729529B1

    公开(公告)日:2023-08-15

    申请号:US17825797

    申请日:2022-05-26

    CPC classification number: H04N25/75 H04N25/53 H04N25/62 H04N25/65 H04N25/771

    Abstract: A global shutter readout circuit includes a reset transistor coupled between a reset voltage and a bitline. A pixel enable transistor is coupled between the reset transistor and a source follower transistor. First and second terminals of the pixel enable transistor are coupled together in response to a pixel enable signal coupled to a third terminal of the pixel enable transistor. A first storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor. A first storage capacitor is coupled to the first storage transistor. A second storage transistor coupled to the second terminal of the pixel enable transistor and the gate of the source follower transistor. A second storage capacitor is coupled to the second storage transistor. A row select transistor is coupled to the source follower transistor to generate an output signal from the global shutter readout circuit.

    DIGITAL TIME STAMPING DESIGN FOR EVENT DRIVEN PIXEL

    公开(公告)号:US20220239858A1

    公开(公告)日:2022-07-28

    申请号:US17156290

    申请日:2021-01-22

    Abstract: An event driven pixel includes a photodiode configured to photogenerate charge in response to incident light received from an external scene. A photocurrent to voltage converter is coupled to the photodiode to convert photocurrent generated by the photodiode to a voltage. A filter amplifier is coupled to the photocurrent to voltage converter to generate a filtered and amplified signal in response to the voltage received from the photocurrent to voltage converter. A threshold comparison stage is coupled to the filter amplifier to compare the filtered and amplified signal received from the filter amplifier with thresholds to asynchronously detect events in the external scene in response to the incident light. A digital time stamp generator is coupled to asynchronously generate a digital time stamp in response to the events asynchronously detected in the external scene by the threshold comparison stage.

    EVENT DRIVEN PIXEL FOR SPATIAL INFORMATION EXTRACTION

    公开(公告)号:US20220199671A1

    公开(公告)日:2022-06-23

    申请号:US17125619

    申请日:2020-12-17

    Abstract: An event driven sensor includes an arrangement of photodiodes including an inner portion laterally surrounded by an outer portion. An outer pixel cell circuit is coupled to generate an outer pixel value in response to photocurrent generated by the outer portion. The outer pixel value is a binned signal representative of an average value of brightness of incident light on the arrangement of photodiodes. An inner pixel cell circuit is coupled to the inner portion to generate an inner pixel value in response to photocurrent generated by from the inner portion. An event driven circuit is coupled to the outer pixel cell circuit and the inner pixel cell circuit. The event driven circuit is coupled to generate an output signal responsive to an inner brightness indicated by the inner pixel value relative to an outer brightness indicated by the outer pixel value.

    DUAL ROW SELECT PIXEL FOR FAST PIXEL BINNING

    公开(公告)号:US20210360175A1

    公开(公告)日:2021-11-18

    申请号:US17066200

    申请日:2020-10-08

    Abstract: A pixel array includes pixel cells, each including photodiodes. A source follower is coupled to generate an image signal in response image charge generated by the photodiodes. A first row select transistor is coupled to the source follower to output the image signal of the pixel cell. Pixel cells are organized into columns including a first column and a second column. The first row select transistors of the pixel cells of the first and second columns of pixel cells are coupled to first and second column bitlines, respectively. The pixel cells of the second column of pixel cells further include a second row select transistor coupled to the source follower to output the respective image signal to the first column bitline.

Patent Agency Ranking