公开(公告)号：US07969815B2

公开(公告)日：2011-06-28

申请号：US12956791

申请日：2010-11-30

申请人： Paul A. LaBerge

发明人： Paul A. LaBerge

IPC分类号： G11C8/00

CPC分类号： H03K5/06 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012

摘要： The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs of a plurality of latches. A phase interpolator is included in a signal path common to all of the branches, and a respective delay line is included in each of the branches. Each of the latches couples a signal applied to its data input to an output terminal responsive to a transition of the digital signal applied to its clock input. The delay lines are adjusted so that the latches are simultaneously clocked. The delay of the phase interpolator is adjusted so that the signals are coupled to the output terminals of the latches with a predetermined timing relationship relative to signals coupled to output terminals of a second signal distribution tree.

摘要翻译： 可以通过将数字信号通过从输入节点延伸到多个锁存器的相应时钟输入的多个分支的信号分配树进行耦合来控制输出信号的定时。 相位插值器被包括在所有分支共用的信号路径中，并且每个分支中包括相应的延迟线。 每个锁存器响应于施加到其时钟输入的数字信号的转变而将施加到其数据输入的信号耦合到输出端子。 延迟线被调整，使得锁存器同时被计时。 调整相位内插器的延迟，使得信号以相对于耦合到第二信号分配树的输出端的信号的预定定时关系耦合到锁存器的输出端。

公开(公告)号：US20100005238A1

公开(公告)日：2010-01-07

申请号：US12261942

申请日：2008-10-30

申请人： Joe M. Jeddeloh ,  Paul A. LaBerge

发明人： Joe M. Jeddeloh ,  Paul A. LaBerge

IPC分类号： G06F13/00

CPC分类号： G06F13/1668 ,  G06F13/1684 ,  G06F13/4022 ,  G06F2213/16 ,  Y02D10/14 ,  Y02D10/151

摘要： Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.

摘要翻译： 本文公开的系统和方法基本上同时传送跨越一个或多个发起设备或诸如处理器和交换机的目的地设备之间的对应多个串行化通信链路接口（SCLI）的多个命令，地址和/或数据流。 在交换机上，可以将与每个流相对应的一个或多个命令，地址或数据传送到与对应的存储器保险库相关联的对应的目的地存储器保管库控制器（MVC）。 目的地MVC可以独立于与耦合到对应的多个存储器库的其他MVC相关联的并行操作执行写入操作，读取操作和/或存储器保管库内务处理操作。

公开(公告)号：US07594088B2

公开(公告)日：2009-09-22

申请号：US11418897

申请日：2006-05-04

申请人： Paul A. LaBerge

发明人： Paul A. LaBerge

IPC分类号： G06F12/00

CPC分类号： G06F13/1689 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1093 ,  G11C7/22 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012

摘要： A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made.

摘要翻译： 一种用于促进在第一时钟域中操作的存储器控​​制器与在第二时钟域中操作的存储器件之间调整定时参数的系统和方法。 监视写指针和读指针以提供写读指针偏移量，表示当存储器设备使读数据可用时和存储器控制器检索读数据时的定时。 基于写指针偏移，可以对不同的定时参数进行调整。

公开(公告)号：US07355387B2

公开(公告)日：2008-04-08

申请号：US11297901

申请日：2005-12-08

申请人： Paul A. LaBerge

发明人： Paul A. LaBerge

IPC分类号： G01R31/28

CPC分类号： G01R31/31905

摘要： An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit includes circuitry for testing the timing margins of memory devices by determining the relative timing between read data and data strobe signals applied to a memory device. The relative timing between the read data and data strobe signals is determined by using a delay line to delay the data strobe signal over a range of delays, and determining a final delay that causes the transitions of the delayed data strobe signal to coincide with the transitions of the read data signals. The time corresponding to the final delay is then determined by using a phase interpolator to generate a range of phase offset signals having known delay times until a phase offset signal has the same delay as the final delay.

摘要翻译： 集成电路负载板包括其上安装有多个集成电路插座和集成测试电路的基板。 集成测试电路包括用于通过确定读取数据和施加到存储器件的数据选通信号之间的相对定时来测试存储器件的定时裕度的电路。 读取数据和数据选通信号之间的相对定时是通过使用延迟线在延迟范围内延迟数据选通信号来确定的，并且确定导致延迟数据选通信号的转变与转换相一致的最终延迟 的读取数据信号。 然后通过使用相位内插器来确定对应于最终延迟的时间，以产生具有已知延迟时间的相位偏移信号的范围，直到相位偏移信号具有与最终延迟相同的延迟。

公开(公告)号：US07284169B2

公开(公告)日：2007-10-16

申请号：US11298163

申请日：2005-12-08

申请人： Paul A. LaBerge ,  Keith J. Lunzer

发明人： Paul A. LaBerge ,  Keith J. Lunzer

IPC分类号： G11C29/00 ,  G06F11/00

CPC分类号： G11C29/56 ,  G11C29/50 ,  G11C29/56012 ,  G11C2029/5602

摘要： Write strobe preamble/postamble test circuitry includes a test signal generator generating first and second digital signals. Also included are a pair of phase interpolators for varying the transition times of respective transmitter clock signals. When enabled, a transmitter uses the transmitter clock signals to transmit a write data strobe signal corresponding to the first and second digital signals to memory devices being tested. The transmitter is enabled by an enable signal generated by a third phase interpolator. By varying the timing of the enable signal, the third phase interpolator can vary the duration of preambles and postambles of respective write data strobe signals.

摘要翻译： 写选通前导码/后同步码测试电路包括产生第一和第二数字信号的测试信号发生器。 还包括用于改变各个发射机时钟信号的转换时间的一对相位内插器。 当使能时，发射机使用发射机时钟信号将对应于第一和第二数字信号的写入数据选通信号发送到被测试的存储器件。 发射机由第三相位内插器产生的使能信号使能。 通过改变使能信号的定时，第三相位内插器可以改变各个写数据选通信号的前同步码和后同步码的持续时间。

公开(公告)号：US07055012B2

公开(公告)日：2006-05-30

申请号：US10930444

申请日：2004-08-31

申请人： Paul A. LaBerge ,  Jeff W. Janzen

发明人： Paul A. LaBerge ,  Jeff W. Janzen

IPC分类号： G06F12/00

CPC分类号： G06F13/4243

摘要： A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory devices and a memory controller is provided. Because different memory devices may have different CAS latencies, a system CAS latency is selected wherein the system CAS latency is the fastest common CAS latency of each of the plurality of memory devices. After a read request is delivered to a memory device, the memory controller initiates a transmission flag to the memory device at a time equal to the system CAS latency, indicating that it is safe to transmit the requested data from the memory device to the memory controller. The transmission flags may be used in conjunction with mode registers such that one or both of the transmission flag and the data may be received by or delivered by a corresponding memory device.

摘要翻译： 一种在系统中选择CAS延迟的方法。 具体地，提供了包括多个存储器件和存储器控制器的系统。 由于不同的存储器件可能具有不同的CAS延迟，因此选择系统CAS等待时间，其中系统CAS等待时间是多个存储器件中每一个的最快的公共​​CAS等待时间。 在将读取请求传送到存储器件之后，存储器控制器在与系统CAS等待时间相等的时间向存储器件发起发送标志，指示可以将所请求的数据从存储器件传送到存储器控制器 。 发送标志可以与模式寄存器一起使用，使得发送标志和数据中的一个或两个可以由相应的存储器件接收或由相应的存储器件传送。

公开(公告)号：US06851032B2

公开(公告)日：2005-02-01

申请号：US10222456

申请日：2002-08-16

申请人： Paul A. LaBerge ,  Jeff W. Janzen

发明人： Paul A. LaBerge ,  Jeff W. Janzen

IPC分类号： G06F12/00 ,  G06F13/42

CPC分类号： G06F13/4243

摘要： A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory devices and a memory controller is provided. Because different memory devices may have different CAS latencies, a system CAS latency is selected wherein the system CAS latency is the fastest common CAS latency of each of the plurality of memory devices. After a read request is delivered to a memory device, the memory controller initiates a transmission flag to the memory device at a time equal to the system CAS latency, indicating that it is safe to transmit the requested data from the memory device to the memory controller. The transmission flags may be used in conjunction with mode registers such that one or both of the transmission flag and the data may be received by or delivered by a corresponding memory device.

摘要翻译： 一种在系统中选择CAS延迟的方法。 具体地，提供了包括多个存储器件和存储器控制器的系统。 由于不同的存储器件可能具有不同的CAS延迟，因此选择系统CAS等待时间，其中系统CAS等待时间是多个存储器件中每一个的最快的公共​​CAS等待时间。 在将读取请求传送到存储器件之后，存储器控制器在与系统CAS等待时间相等的时间向存储器件发起发送标志，指示可以将所请求的数据从存储器件传送到存储器控制器 。 发送标志可以与模式寄存器一起使用，使得发送标志和数据中的一个或两个可以由相应的存储器件接收或由相应的存储器件传送。

公开(公告)号：US06804764B2

公开(公告)日：2004-10-12

申请号：US10054556

申请日：2002-01-22

申请人： Paul A. LaBerge ,  Jim Dodd

发明人： Paul A. LaBerge ,  Jim Dodd

IPC分类号： G06F1200

CPC分类号： G06F13/4243 ,  G06F13/1694

摘要： A configuration register used to adjust a clock or request signal with respect to the other. Specifically, a look-up table is provided in the memory controller. The look-up table is filled at bootup such that it contains test information from a master look-up table in the system BIOS, for instance. The look-up table in the memory controller stores current test data correlative to optimal sampling times for the current configuration. Adjustable delay elements or adjustable load elements may be used to change the relative sampling time of the request signal correlative to the values stored in the memory controller look-up table.

摘要翻译： 用于调整相对于另一个的时钟或请求信号的配置寄存器。 具体地，在存储器控制器中提供查找表。 查找表在引导时被填充，例如，它包含来自系统BIOS中的主查找表的测试信息。 存储器控制器中的查找表存储与当前配置的最佳采样时间相关的当前测试数据。 可调节的延迟元件或可调负载元件可用于改变与存储在存储器控制器查找表中的值相关的请求信号的相对采样时间。

公开(公告)号：US06795931B1

公开(公告)日：2004-09-21

申请号：US09409367

申请日：1999-09-30

申请人： Paul A. LaBerge

发明人： Paul A. LaBerge

IPC分类号： G06F112

CPC分类号： H03K5/133 ,  H03K2005/00058 ,  H03K2005/00156

摘要： A programmable delay circuit having a plurality of course delay stages (coupled in series fashion) and a fine delay stage having a plurality of parallel organized delay paths is described, wherein each of the parallel organized delay paths is adapted to receive input from a common course delay stage and to delay a signal for a different specified amount of time. The programmable delay circuit may provide a relatively large overall signal delay (provided primarily by the course delay stages), while also providing a fine temporal resolution (provided primarily by the fine delay stage).

摘要翻译： 描述了具有多个行程延迟级（以串联方式耦合）的可编程延迟电路和具有多个并行有组织的延迟路径的精细延迟级，其中每个并行组织的延迟路径适于接收来自公共过程的输入 延迟阶段，并延迟信号达到不同的指定时间量。 可编程延迟电路可以提供相对较大的总体信号延迟（主要由课程延迟阶段提供），同时还提供精细的时间分辨率（主要由精细延迟阶段提供）。

公开(公告)号：US06732342B2

公开(公告)日：2004-05-04

申请号：US09829857

申请日：2001-04-09

申请人： Paul A. LaBerge

发明人： Paul A. LaBerge

IPC分类号： G06F1750

CPC分类号： G06F17/5072

摘要： One embodiment of the present invention provides a system that creates a layout of a circuit by placing gates at specific locations in a circuit design based upon drive strengths and wireloads of gates in the circuit. The system operates on a gate-level description of the circuit, which includes a specification of gates in the circuit and a specification of a set of interconnections between the gates. From this gate-level description, the system obtains drive strength information for specific gates in the circuit, and uses this drive strength information as a factor in optimizing a placement for the gates in order to meet a set of timing constraints. The system may also use wireload information—in addition to the drive strength information—to place the gates. A variation on the above embodiment subsequently performs a timing-based placement operation to further optimize the drive strength-based placement. Another variation associates weights with drive strengths for individual gates. These weights are fed into a standard placement function, such as a quadratic placement function or a simulated annealing function, to produce a placement for the gates. Thus, the present invention achieves a better placement of gates than a conventional connectivity-based placement system that merely considers the number of connections to a gate.

摘要翻译： 本发明的一个实施例提供了一种通过基于电路中的栅极的驱动强度和有线负载将门放置在电路设计中的特定位置处来创建电路布局的系统。 该系统对电路的栅极级描述进行操作，其包括电路中的栅极的规格以及栅极之间的一组互连的规格。 从该门级描述中，系统获得电路中特定门的驱动强度信息，并且使用该驱动强度信息作为优化门的放置的因素，以满足一组时序约束。 除了驱动强度信息之外，系统还可以使用有线负载信息来放置门。 上述实施例的变型随后执行基于时序的布置操作，以进一步优化基于驱动强度的布置。 另一个变体将权重与个别门的驱动力相结合。 这些权重被馈送到诸如二次放置函数或模拟退火函数的标准放置函数中，以产生用于门的放置。 因此，与仅考虑到与门的连接数目的常规基于连接的放置系统相比，本发明实现了门的更好的布置。