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公开(公告)号：US08741713B2
公开(公告)日：2014-06-03
申请号：US13572245
申请日：2012-08-10
IPC分类号： H01L21/336
CPC分类号： H01L23/57 , G06F7/588 , G06F21/73 , G09C1/00 , H01L22/34 , H01L2924/0002 , H04L9/0866 , H01L2924/00
摘要： The present disclosure relates to a secure device having a physical unclonable function and methods of manufacturing such a secure device. The device includes a substrate and at least one high-k/metal gate device formed on the substrate. The at least one high-k/metal gate device represents the physical unclonable function. In some cases, the at least one high-k/metal gate device may be subjected a variability enhancement. In some cases, the secure device may include a measurement circuit for measuring a property of the at least one high-k/metal gate device.
摘要翻译： 本公开涉及具有物理不可克隆功能的安全装置和制造这种安全装置的方法。 该器件包括衬底和形成在衬底上的至少一个高k /金属栅极器件。 至少一个高k /金属栅极器件表示物理不可克隆功能。 在一些情况下，可以对至少一个高k /金属栅极器件进行可变性增强。 在一些情况下，安全装置可以包括用于测量至少一个高k /金属门装置的特性的测量电路。
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52.发明申请ANGULAR SPECTRUM TAILORING IN SOLID IMMERSION MICROSCOPY FOR CIRCUIT ANALYSIS 失效用于电路分析的固体显微镜中的角度光谱定标公开(公告)号：US20110037973A1
公开(公告)日：2011-02-17
申请号：US12911781
申请日：2010-10-26
IPC分类号： G01N21/88
CPC分类号： G01R31/311
摘要： A structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.
摘要翻译： 用于定位半导体芯片中的故障的结构。 芯片包括电介质互连上的衬底。 包括代表故障的点的芯片的第一电响应图像重叠在从光学显微镜通过SIL / NAIL并进入芯片的光路中的单色光的第一反射图像上。 衬底的折射率超过电介质互连的折射率，等于SIL / NAIL的折射率。 芯片的第二电响应图像覆盖在光路中的单色光的第二反射图像上，其中光学停止器防止单色光的所有亚临界角分量入射到SIL / NAIL上。 如果第二电响应图像包括或不包括点，则故障分别在基板或电介质互连中。
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公开(公告)号：US20100109700A1
公开(公告)日：2010-05-06
申请号：US12684142
申请日：2010-01-08
IPC分类号： G01R31/36
CPC分类号： G01R31/30 , G01R31/2884 , G01R31/3016 , G01R31/31721
摘要： On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outside a user-defined threshold are detected. The undershoots and overshoots are indicated by a relative difference in phase of the two delay chains. The two delay chains are programmable to detect various frequencies.
摘要翻译： 片上传感器检测电源漏洞。 片内传感器采用敏感延迟链和不敏感延迟链，以检测电源下冲和过冲，而无需外部片外部件。 检测到用户定义的阈值之外的下冲和超调。 下冲和过冲由两个延迟链的相位相对差异表示。 两个延迟链可编程，以检测各种频率。
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54.发明授权公开(公告)号：US07089474B2
公开(公告)日：2006-08-08
申请号：US10789710
申请日：2004-02-27
申请人： Todd M. Burdine , Franco Motika , Peilin Song
发明人： Todd M. Burdine , Franco Motika , Peilin Song
CPC分类号： G06F11/261 , G01R31/31703 , G01R31/318371 , G06F11/263
摘要： A method for providing interactive and iterative testing of integrated circuits including the receiving of a first failing region. The first failing region corresponds to one or more circuits on the integrated circuit. The method generates a set of adaptive algorithmic test patterns for the one or more circuits in response to the first failing region and to a logic model of the integrated circuit. Expected results for the test patterns are determined. The method includes applying the test patterns to the first failing region on the integrated circuit resulting in actual results for the test patterns. The expected results to the actual results are compared. The method also transmits mismatches between the expected results and the actual results to a fault simulator. The method includes receiving a second failing region from the fault simulator, the second failing region created in response to the mismatches and the logic model, and the second failing region corresponding to a subset of the one or more circuits on the integrated circuit.
摘要翻译： 一种用于提供集成电路的交互式和迭代测试的方法，包括接收第一故障区域。 第一故障区域对应于集成电路上的一个或多个电路。 该方法响应于第一故障区域和集成电路的逻辑模型生成针对一个或多个电路的一组自适应算法测试模式。 确定测试模式的预期结果。 该方法包括将测试图案应用于集成电路上的第一故障区域，从而得到测试图案的实际结果。 对实际结果的预期结果进行比较。 该方法还将预期结果与实际结果之间的错配传输到故障模拟器。 该方法包括从故障模拟器接收第二故障区域，响应于不匹配和逻辑模型而创建的第二故障区域，以及对应于集成电路上的一个或多个电路的子集的第二故障区域。
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公开(公告)号：US06662324B1
公开(公告)日：2003-12-09
申请号：US09642371
申请日：2000-08-21
IPC分类号： G01R3128
CPC分类号： G01R31/318525 , G01R31/31853 , G01R31/31858
摘要： The present invention, enables complementing the state of either the master (L1) or slave latch (L2) in the shift register latches (SRLs) without changing the state of the other. When this is done after properly loading the LSSD scan chain using a normal scan chain sequence, the next system clock sequence can be used to launch a desired transition from each SRL in the scan chain. The actual mechanism for complementing the state of latches in LSSD scan chains can vary depending on which one of the L1 or L2 latch is being complemented; details of the actual scan chain and Shift Register Latch (SRL) design; and the semiconductor chip circuit technology. The complementing function can be provided as an integral part of the SRL design with minimal impact to system path and performance. An alternate complementing method would be to use a self complementing latch function. In this design, the latch to be complemented does not require an additional input containing the complement value, but rather uses its current state as reference and switches to the opposite state. To accomplish this, a complement signal similar to a latch reset (i.e., reset-to-complement) can be used.
摘要翻译： 本发明能够在不改变另一个状态的情况下补充移位寄存器锁存器（SRL）中的主（L1）或从锁存器（L2）的状态。 当使用正常扫描链序列正确加载LSSD扫描链后，可以使用下一个系统时钟序列来启动扫描链中每个SRL所需的转换。 补充LSSD扫描链中锁存器状态的实际机制可以根据L1或L2锁存器中的哪一个进行补充而变化; 实际扫描链和Shift Register Latch（SRL）设计的细节; 和半导体芯片电路技术。 补充功能可以作为SRL设计的一个组成部分提供，对系统路径和性能影响最小。 一种替代的补充方法是使用自补充锁存功能。 在这种设计中，要补充的锁存器不需要包含补码值的附加输入，而是使用其当前状态作为参考，并切换到相反的状态。 为了实现这一点，可以使用类似于锁存器复位（即，复位到补码）的补码信号。
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56.发明授权Technique to decrease the exposure time of infrared imaging of semiconductor chips for failure analysis 失效降低半导体芯片红外成像曝光时间的技术进行故障分析公开(公告)号：US06442720B1
公开(公告)日：2002-08-27
申请号：US09326226
申请日：1999-06-04
IPC分类号： G01R3128
CPC分类号： G01R31/31858
摘要： The present invention can include a method and system for testing IC chips, including the steps of performing a binary search to a first failing pattern, determining a failing sink latch, performing a back cone trace to determine all source latches, determining source latch logic states, positioning the source latch logic states in a scan chain, exercising a chip scan path by applying logic transitions on the source latches in the absence of a system L1 clock, and observing an exercised failing circuit. The invention can include the use of PICA techniques to observe the exercised failing circuit. In another embodiment, the invention can include using LBIST or a WRP technique to search for the failing pattern. In yet another it includes the step of using an algorithm to exercise the exercised failing circuit. In another embodiment, the method includes the step of creating a net pattern to be scanned including a sum of an original pattern causing a failing circuit to be exercised, and one or more shifted versions of the original pattern. The algorithm can include a step where one of the shifted versions is shifted a number of clocks wherein the number of clocks is equal to the length of the original pattern. In one embodiment, one of the shifted versions is shifted a number of clocks, wherein the number of clocks is chosen so that the sum of the original pattern and the one of the shifted versions does not cause a scan conflict. In another embodiment the method further includes the step of using an algorithm to densify the pattern set.
摘要翻译： 本发明可以包括用于测试IC芯片的方法和系统，包括以下步骤：对第一故障模式执行二进制搜索，确定故障接收器锁存器，执行后锥迹线以确定所有源锁存器，确定源锁存器逻辑状态 将源锁存器逻辑状态定位在扫描链中，通过在没有系统L1时钟的情况下在源锁存器上施加逻辑转换并观察行使的故障电路来执行芯片扫描路径。 本发明可以包括使用PICA技术来观察行使的故障电路。 在另一个实施例中，本发明可以包括使用LBIST或WRP技术来搜索失败的模式。 在另一方面，它包括使用算法来锻炼锻炼的故障电路的步骤。 在另一个实施例中，该方法包括创建要被扫描的网络图案的步骤，包括导致执行故障电路的原始图案的和以及原始图案的一个或多个偏移版本。 该算法可以包括一个步骤，其中移位版本中的一个被移位了多个时钟，其中时钟数等于原始图案的长度。 在一个实施例中，移位版本中的一个被移位了多个时钟，其中选择时钟的数量，使得原始模式和移位版本之一的总和不会引起扫描冲突。 在另一个实施例中，该方法还包括使用算法来密集模式集的步骤。
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公开(公告)号：US20140042442A1
公开(公告)日：2014-02-13
申请号：US13572245
申请日：2012-08-10
CPC分类号： H01L23/57 , G06F7/588 , G06F21/73 , G09C1/00 , H01L22/34 , H01L2924/0002 , H04L9/0866 , H01L2924/00
摘要： The present disclosure relates to a secure device having a physical unclonable function and methods of manufacturing such a secure device. The device includes a substrate and at least one high-k/metal gate device formed on the substrate. The at least one high-k/metal gate device represents the physical unclonable function. In some cases, the at least one high-k/metal gate device may be subjected a variability enhancement. In some cases, the secure device may include a measurement circuit for measuring a property of the at least one high-k/metal gate device.
摘要翻译： 本公开涉及具有物理不可克隆功能的安全装置和制造这种安全装置的方法。 该器件包括衬底和形成在衬底上的至少一个高k /金属栅极器件。 至少一个高k /金属栅极器件表示物理不可克隆功能。 在一些情况下，可以对至少一个高k /金属栅极器件进行可变性增强。 在一些情况下，安全装置可以包括用于测量至少一个高k /金属门装置的特性的测量电路。
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公开(公告)号：US07952370B2
公开(公告)日：2011-05-31
申请号：US12684142
申请日：2010-01-08
IPC分类号： G01R31/40 , G01R31/3187
CPC分类号： G01R31/30 , G01R31/2884 , G01R31/3016 , G01R31/31721
摘要： On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outside a user-defined threshold are detected. The undershoots and overshoots are indicated by a relative difference in phase of the two delay chains. The two delay chains are programmable to detect various frequencies.
摘要翻译： 片上传感器检测电源漏洞。 片内传感器采用敏感延迟链和不敏感延迟链，以检测电源下冲和过冲，而无需外部片外部件。 检测到用户定义的阈值之外的下冲和超调。 下冲和过冲由两个延迟链的相位相对差异表示。 两个延迟链可编程，以检测各种频率。
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公开(公告)号：US07646208B2
公开(公告)日：2010-01-12
申请号：US12013833
申请日：2008-01-14
CPC分类号： G01R31/30 , G01R31/2884 , G01R31/3016 , G01R31/31721
摘要： On-chip sensor to detect power supply vulnerabilities. The on-chip sensor employs a sensitive delay chain and an insensitive delay chain to detect power supply undershoots and overshoots without requiring external off-chip components. Undershoots and overshoots outside a user-defined threshold are detected. The undershoots and overshoots are indicated by a relative difference in phase of the two delay chains. The two delay chains are programmable to detect various frequencies.
摘要翻译： 片上传感器检测电源漏洞。 片内传感器采用敏感延迟链和不敏感延迟链，以检测电源下冲和过冲，而无需外部片外部件。 检测到用户定义的阈值之外的下冲和超调。 下冲和过冲由两个延迟链的相位相对差异表示。 两个延迟链可编程，以检测各种频率。
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公开(公告)号：US07443187B2
公开(公告)日：2008-10-28
申请号：US11874528
申请日：2007-10-18
申请人： Keith A. Jenkins , Anuja Sehgal , Peilin Song
发明人： Keith A. Jenkins , Anuja Sehgal , Peilin Song
IPC分类号： G01R31/02
CPC分类号： G01R31/3004 , G01R19/16552
摘要： Techniques for on-chip detection of integrated circuit power supply noise are disclosed. By way of example, a technique for monitoring a power supply line in an integrated circuit includes the following steps/operations. A first signal and a second signal are preconditioned. The first signal is representative of a voltage of the power supply line being monitored. The second signal is representative of a voltage of a reference power supply line. Preconditioning includes shifting respective levels of the voltages such that the voltages are within an input voltage range of comparator circuitry. Then, the preconditioned first signal and the preconditioned second signal are compared in accordance with the comparator circuitry. Comparison includes detecting when a difference exists between the voltage level of the preconditioned first signal and the voltage level of the preconditioned second signal.
摘要翻译： 公开了片上检测集成电路电源噪声的技术。 作为示例，用于监视集成电路中的电源线的技术包括以下步骤/操作。 第一信号和第二信号被预处理。 第一信号代表被监测的电源线的电压。 第二信号代表参考电源线的电压。 预处理包括移动电压的各个电平，使得电压在比较器电路的输入电压范围内。 然后，根据比较器电路对预处理的第一信号和预处理的第二信号进行比较。 比较包括检测预处理的第一信号的电压电平与预处理的第二信号的电压电平之间的差异。
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