公开(公告)号：US20140042442A1

公开(公告)日：2014-02-13

申请号：US13572245

申请日：2012-08-10

申请人： JOHN BRULEY ,  Vijay Narayanan ,  Dirk Pfeiffer ,  Jean-Oliver Plouchart ,  Peilin Song

发明人： JOHN BRULEY ,  Vijay Narayanan ,  Dirk Pfeiffer ,  Jean-Oliver Plouchart ,  Peilin Song

IPC分类号： H01L23/58 ,  H01L21/66

CPC分类号： H01L23/57 ,  G06F7/588 ,  G06F21/73 ,  G09C1/00 ,  H01L22/34 ,  H01L2924/0002 ,  H04L9/0866 ,  H01L2924/00

摘要： The present disclosure relates to a secure device having a physical unclonable function and methods of manufacturing such a secure device. The device includes a substrate and at least one high-k/metal gate device formed on the substrate. The at least one high-k/metal gate device represents the physical unclonable function. In some cases, the at least one high-k/metal gate device may be subjected a variability enhancement. In some cases, the secure device may include a measurement circuit for measuring a property of the at least one high-k/metal gate device.

摘要翻译： 本公开涉及具有物理不可克隆功能的安全装置和制造这种安全装置的方法。 该器件包括衬底和形成在衬底上的至少一个高k /金属栅极器件。 至少一个高k /金属栅极器件表示物理不可克隆功能。 在一些情况下，可以对至少一个高k /金属栅极器件进行可变性增强。 在一些情况下，安全装置可以包括用于测量至少一个高k /金属门装置的特性的测量电路。

公开(公告)号：US20050045819A1

公开(公告)日：2005-03-03

申请号：US10604989

申请日：2003-08-29

申请人： Stephen Bedell ,  John Bruley ,  Anthony Domenicucci ,  Devendra Sadana

发明人： Stephen Bedell ,  John Bruley ,  Anthony Domenicucci ,  Devendra Sadana

IPC分类号： G01N1/28 ,  G01N23/04 ,  H01J37/26 ,  G01D18/00

CPC分类号： G01N23/04 ,  G01N2001/2893 ,  H01J37/261 ,  H01J2237/2826

摘要： A method and calibration standard for fabricating on a single substrate a series of crystalline pairs such that the d-spacing difference between the pairs will generate Moire fringes of the correct spacings to optimally calibrate the magnification settings of an electron microscope over a variety of magnification settings in the range of 5000× to 200,000×. The invention enables the tailoring of Moire fringe spacings to a desired magnification setting for calibration purposes by fabricating a series of patterns on a single substrate whereby each magnification setting is easily calibrated using a specific SGOI structure that is selected by a simple x-y translation across the top plan surface of the SGOI structure, therein eliminating the need for removing calibration samples in and out of the electron microscope. The method and calibration standard may be used for calibrating electron microscopes, such as, scanning transmission electron microscopes and transmission electron microscopes.

摘要翻译： 一种用于在单个基板上制造一系列晶体对的方法和校准标准，使得对之间的d间距差会产生正确间隔的莫尔条纹，以便通过各种放大设置最佳地校准电子显微镜的放大倍率设置 在5000x到200,000x的范围内。 通过在单个基板上制造一系列图案，本发明可以通过在单个基板上制造一系列图案来将莫尔条纹间距定制到所需的放大倍率设置，从而可以使用特定的SGOI结构轻松校准每个放大倍数设置，该SGOI结构通过顶部的简单xy平移 SGOI结构的平面表面，其中不需要将校准样品移入和移出电子显微镜。 该方法和校准标准可用于校准电子显微镜，例如扫描透射电子显微镜和透射电子显微镜。

公开(公告)号：US20120228773A1

公开(公告)日：2012-09-13

申请号：US13042618

申请日：2011-03-08

申请人： Stephen L. Brown ,  John Bruley ,  Cyril Cabral, JR. ,  Sandro Callegari ,  Martin M. Frank ,  Michael A. Guillorn ,  Marinus Hopstaken ,  Vijay Narayanan ,  Keith Kwong Hon Wong

发明人： Stephen L. Brown ,  John Bruley ,  Cyril Cabral, JR. ,  Sandro Callegari ,  Martin M. Frank ,  Michael A. Guillorn ,  Marinus Hopstaken ,  Vijay Narayanan ,  Keith Kwong Hon Wong

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L23/53266 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A layered structure and semiconductor device and methods for fabricating a layered structure and semiconductor device. The layered structure includes: a base layer including a material containing titanium nitride, tantalum nitride, or a combination thereof; a conductive layer including a material containing: tantalum aluminum nitride, titanium aluminum nitride, tantalum silicon nitride, titanium silicon nitride, tantalum hafnium nitride, titanium hafnium nitride, hafnium nitride, hafnium carbide, tantalum carbide, vanadium nitride, niobium nitride, or any combination thereof; and a tungsten layer. The semiconductor device includes: a semiconductor substrate; a base layer; a conductive layer; and a tungsten layer.

公开(公告)号：US20060160350A1

公开(公告)日：2006-07-20

申请号：US11037970

申请日：2005-01-18

申请人： John Bruley ,  Roy Carruthers ,  Lynne Gignac ,  Chao-Kun Hu ,  Eric Liniger ,  Sandra Malhotra ,  Stephen Rossnagel

发明人： John Bruley ,  Roy Carruthers ,  Lynne Gignac ,  Chao-Kun Hu ,  Eric Liniger ,  Sandra Malhotra ,  Stephen Rossnagel

IPC分类号： H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Disclosed is a procedure to coat the free surface of Cu damascene lines by a 1-5 nm thick element prior to deposition of the inter-level dielectric or dielectric diffusion barrier layer. The coating provides protection against oxidation, increases the adhesion strength between the Cu and dielectric, and reduces interface diffusion of Cu. In addition, the thin cap layer further increases electromigration Cu lifetime and reduces the stress induced voiding. The selective elements can be directly deposited onto the Cu embedded within the under layer dielectric without causing an electric short circuit between the Cu lines. These chosen elements are based on their high negative reduction potentials with oxygen and water, and a low solubility in and formation of compounds with Cu.

摘要翻译： 公开了在沉积层间电介质或电介质扩散阻挡层之前，通过1-5nm厚的元件涂覆Cu镶嵌线的自由表面的步骤。 涂层提供防氧化保护，增加Cu和介电层之间的粘合强度，并减少Cu的界面扩散。 此外，薄盖层进一步增加电迁移Cu寿命，并减少应力引起的空隙。 选择元件可以直接沉积在嵌入在下层电介质中的Cu上，而不会在Cu线之间引起电短路。 这些选择的元素是基于它们具有氧和水的高的负还原电位，以及与Cu的化合物的低溶解度和形成。

公开(公告)号：US06878624B1

公开(公告)日：2005-04-12

申请号：US10674645

申请日：2003-09-30

申请人： John Bruley ,  Cyril Cabral, Jr. ,  Christian Lavoie ,  Tina J. Wagner ,  Yun Yu Wang ,  Horati S. Wildman ,  Wong Kwong Hon

发明人： John Bruley ,  Cyril Cabral, Jr. ,  Christian Lavoie ,  Tina J. Wagner ,  Yun Yu Wang ,  Horati S. Wildman ,  Wong Kwong Hon

IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L21/768 ,  H01L23/52

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76855 ,  H01L21/76856 ,  H01L29/665

摘要： The present invention provides a method for forming an interconnect to a cobalt or nickel silicide having a TiN diffusion barrier. The inventive method comprises providing an initial structure having vias to exposed silicide regions positioned on a substrate; annealing the initial structure in a nitrogen-containing ambient, wherein a nitrogen passivation layer is formed atop the exposed silicide region; depositing Ti atop the nitrogen passivation layer; annealing the Ti in a nitrogen-containing ambient to form a TiN diffusion barrier and an amorphous Ti cobalt silicide between the TiN diffusion layer and the cobalt or nickel silicide and depositing an interconnect metal within the vias and atop the TiN diffusion barrier. The nitrogen passivation layer substantially restricts diffusion between the Ti and silicide layers minimizing the amorphous Ti cobalt silicide layer that forms. Therefore, the amorphous Ti cobalt or Ti nickel silicide is restricted to a thickness of less than about 3.0 nm.

摘要翻译： 本发明提供一种用于形成具有TiN扩散阻挡层的钴或镍硅化物的互连的方法。 本发明的方法包括提供具有通孔的初始结构，以暴露出位于基板上的硅化物区域; 在含氮环境中退火初始结构，其中在暴露的硅化物区域上形成氮钝化层; 在氮钝化层顶上沉积Ti; 在含氮环境中退火Ti以在TiN扩散层和钴或镍硅化物之间形成TiN扩散阻挡层和非晶Ti钴硅化物，并在通孔内和TiN扩散势垒顶上沉积互连金属。 氮钝化层基本上限制了Ti和硅化物层之间的扩散，使形成的无定形Ti钴硅化物层最小化。 因此，非晶Ti钴或Ti镍硅化物被限制在小于约3.0nm的厚度。

公开(公告)号：US06875982B2

公开(公告)日：2005-04-05

申请号：US10604989

申请日：2003-08-29

申请人： Stephen W. Bedell ,  John Bruley ,  Anthony G. Domenicucci ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  John Bruley ,  Anthony G. Domenicucci ,  Devendra K. Sadana

IPC分类号： G01N1/28 ,  G01N23/04 ,  H01J37/26

CPC分类号： G01N23/04 ,  G01N2001/2893 ,  H01J37/261 ,  H01J2237/2826

摘要： A method and calibration standard for fabricating on a single substrate a series of crystalline pairs such that the d-spacing difference between the pairs will generate Moire fringes of the correct spacings to optimally calibrate the magnification settings of an electron microscope over a variety of magnification settings in the range of 5000× to 200,000×. The invention enables the tailoring of Moire fringe spacings to a desired magnification setting for calibration purposes by fabricating a series of patterns on a single substrate whereby each magnification setting is easily calibrated using a specific SGOI structure that is selected by a simple x-y translation across the top plan surface of the SGOI structure, therein eliminating the need for removing calibration samples in and out of the electron microscope. The method and calibration standard may be used for calibrating electron microscopes, such as, scanning transmission electron microscopes and transmission electron microscopes.

摘要翻译： 一种用于在单个基板上制造一系列晶体对的方法和校准标准，使得对之间的d间距差会产生正确间隔的莫尔条纹，以便通过各种放大设置最佳地校准电子显微镜的放大倍率设置 在5000x到200,000x的范围内。 通过在单个基板上制造一系列图案，本发明可以通过在单个基板上制造一系列图案来将莫尔条纹间距定制到所需的放大倍率设置，从而可以使用特定的SGOI结构轻松校准每个放大倍数设置，该SGOI结构通过顶部的简单xy平移 SGOI结构的平面表面，其中不需要将校准样品移入和移出电子显微镜。 该方法和校准标准可用于校准电子显微镜，例如扫描透射电子显微镜和透射电子显微镜。

公开(公告)号：US20050070098A1

公开(公告)日：2005-03-31

申请号：US10674645

申请日：2003-09-30

申请人： John Bruley ,  Cyril Cabral ,  Christian Lavoie ,  Tina Wagner ,  Yun Wang ,  Horatl Wlldman ,  Wong Hon

发明人： John Bruley ,  Cyril Cabral ,  Christian Lavoie ,  Tina Wagner ,  Yun Wang ,  Horatl Wlldman ,  Wong Hon

IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L21/768 ,  H01L23/52

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76855 ,  H01L21/76856 ,  H01L29/665

摘要： The present invention provides a method for forming an interconnect to a cobalt or nickel silicide having a TiN diffusion barrier. The inventive method comprises providing an initial structure having vias to exposed silicide regions positioned on a substrate; annealing the initial structure in a nitrogen-containing ambient, wherein a nitrogen passivation layer is formed atop the exposed silicide region; depositing Ti atop the nitrogen passivation layer; annealing the Ti in a nitrogen-containing ambient to form a TiN diffusion barrier and an amorphous Ti cobalt silicide between the TiN diffusion layer and the cobalt or nickel silicide and depositing an interconnect metal within the vias and atop the TiN diffusion barrier. The nitrogen passivation layer substantially restricts diffusion between the Ti and silicide layers minimizing the amorphous Ti cobalt silicide layer that forms. Therefore, the amorphous Ti cobalt or Ti nickel silicide is restricted to a thickness of less than about 3.0 nm.

摘要翻译： 本发明提供一种用于形成具有TiN扩散阻挡层的钴或镍硅化物的互连的方法。 本发明的方法包括提供具有通孔的初始结构，以暴露出位于基板上的硅化物区域; 在含氮环境中退火初始结构，其中在暴露的硅化物区域上形成氮钝化层; 在氮钝化层顶上沉积Ti; 在含氮环境中退火Ti以在TiN扩散层和钴或镍硅化物之间形成TiN扩散阻挡层和非晶Ti钴硅化物，并在通孔内和TiN扩散势垒顶上沉积互连金属。 氮钝化层基本上限制了Ti和硅化物层之间的扩散，使形成的无定形Ti钴硅化物层最小化。 因此，非晶Ti钴或Ti镍硅化物被限制在小于约3.0nm的厚度。

公开(公告)号：US20050064610A1

公开(公告)日：2005-03-24

申请号：US10605258

申请日：2003-09-18

申请人： JOHN BRULEY ,  TERENCE KANE ,  MICHAEL TENNEY ,  YUN WANG

发明人： JOHN BRULEY ,  TERENCE KANE ,  MICHAEL TENNEY ,  YUN WANG

IPC分类号： G01R31/307 ,  H01L21/66

CPC分类号： H01L22/24 ,  G01R31/307 ,  H01L2924/0002 ,  Y10S438/902 ,  H01L2924/00

摘要： This invention relates to a method for electrically localizing site-specific defective sub 130 nm node MOSFET devices with shallow (less than 80 nm deep) source/drain junctions utilizing bulk silicon, or Silicon on Insulator (SOI), or strained silicon (SE), followed by optimized sample preparation steps that permits imaging, preferably high resolution electron holographic imaging, in an electron microscope to detect blocked implants, asymmetric doping, or channel length variations affecting MOSFET device performance. Detection of such defects in such shallow junctions enables further refinements in process simulation models and permits optimization of MOSFET device designs.

摘要翻译： 本发明涉及一种利用体硅或绝缘体上硅（SOI）或应变硅（SE）的具有浅（小于80nm深）源极/漏极结的电位定位缺陷子130nm节点MOSFET器件的方法， ，然后进行优化的样品制备步骤，其允许在电子显微镜中成像，优选高分辨率电子全息成像，以检测影响MOSFET器件性能的封闭植入物，不对称掺杂或沟道长度变化。 在这种浅结中的这种缺陷的检测使得能够进一步改进工艺仿真模型并允许优化MOSFET器件设计。

公开(公告)号：US07247946B2

公开(公告)日：2007-07-24

申请号：US11037970

申请日：2005-01-18

申请人： John Bruley ,  Roy A. Carruthers ,  Lynne Marie Gignac ,  Chao-Kun Hu ,  Eric Gerhard Liniger ,  Sandra Guy Malhotra ,  Stephen M. Rossnagel

发明人： John Bruley ,  Roy A. Carruthers ,  Lynne Marie Gignac ,  Chao-Kun Hu ,  Eric Gerhard Liniger ,  Sandra Guy Malhotra ,  Stephen M. Rossnagel

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76849 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Disclosed is a procedure to coat the free surface of Cu damascene lines by a 1-5 nm thick element prior to deposition of the inter-level dielectric or dielectric diffusion barrier layer. The coating provides protection against oxidation, increases the adhesion strength between the Cu and dielectric, and reduces interface diffusion of Cu. In addition, the thin cap layer further increases electromigration Cu lifetime and reduces the stress induced voiding. The selective elements can be directly deposited onto the Cu embedded within the under layer dielectric without causing an electric short circuit between the Cu lines. These chosen elements are based on their high negative reduction potentials with oxygen and water, and a low solubility in and formation of compounds with Cu.

摘要翻译： 公开了在沉积层间电介质或电介质扩散阻挡层之前，通过1-5nm厚的元件涂覆Cu镶嵌线的自由表面的步骤。 涂层提供防氧化保护，增加Cu和介电层之间的粘合强度，并减少Cu的界面扩散。 此外，薄盖层进一步增加电迁移Cu寿命，并减少应力引起的空隙。 选择元件可以直接沉积在嵌入在下层电介质中的Cu上，而不会在Cu线之间引起电短路。 这些选择的元素是基于它们具有氧和水的高的负还原电位，以及与Cu的化合物的低溶解度和形成。

公开(公告)号：US06884641B2

公开(公告)日：2005-04-26

申请号：US10605258

申请日：2003-09-18

申请人： John Bruley ,  Terence Kane ,  Michael P. Tenney ,  Yun Yu Wang

发明人： John Bruley ,  Terence Kane ,  Michael P. Tenney ,  Yun Yu Wang

IPC分类号： G01R31/307 ,  H01L21/66 ,  H01L31/26

CPC分类号： H01L22/24 ,  G01R31/307 ,  H01L2924/0002 ,  Y10S438/902 ,  H01L2924/00

摘要： This invention relates to a method for electrically localizing site-specific defective sub 130 nm node MOSFET devices with shallow (less than 80 nm deep) source/drain junctions utilizing bulk silicon, or Silicon on Insulator (SOI), or strained silicon (SE), followed by optimized sample preparation steps that permits imaging, preferably high resolution electron holographic imaging, in an electron microscope to detect blocked implants, asymmetric doping, or channel length variations affecting MOSFET device performance. Detection of such defects in such shallow junctions enables further refinements in process simulation models and permits optimization of MOSFET device designs.

摘要翻译： 本发明涉及一种利用体硅或绝缘体上硅（SOI）或应变硅（SE）的具有浅（小于80nm深）源极/漏极结的电位定位缺陷子130nm节点MOSFET器件的方法， ，然后进行优化的样品制备步骤，其允许在电子显微镜中成像，优选高分辨率电子全息成像，以检测影响MOSFET器件性能的封闭植入物，不对称掺杂或沟道长度变化。 在这种浅结中的这种缺陷的检测使得能够进一步改进工艺仿真模型并允许优化MOSFET器件设计。