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    SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
    51.
    发明申请
    SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE 有权
    半导体元件及其制造方法

    公开(公告)号：US20080277694A1

    公开(公告)日：2008-11-13

    申请号：US11746437

    申请日：2007-05-09

    申请人： Zia Hossain ,  Francine Y. Robb ,  Prasad Venkatraman

    发明人： Zia Hossain ,  Francine Y. Robb ,  Prasad Venkatraman

    IPC分类号： H01L27/095 ,  H01L21/44 ,  H01L29/76

    CPC分类号： H01L27/0629 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/28537 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/8249

    摘要： A semiconductor component that includes a Schottky device, an edge termination structure, a non-Schottky semiconductor device, combinations thereof and a method of manufacturing the semiconductor component. A semiconductor material includes a first epitaxial layer disposed on a semiconductor substrate and a second epitaxial layer disposed on the first epitaxial layer. The second epitaxial layer has a higher resistivity than the semiconductor substrate. A Schottky device and a non-Schottky semiconductor device are manufactured from the second epitaxial layer. In accordance with another embodiment, a semiconductor material includes an epitaxial layer disposed over a semiconductor substrate. The epitaxial layer has a higher resistivity than the semiconductor substrate. A doped region is formed in the epitaxial layer. A Schottky device and a non-Schottky semiconductor device are manufactured from the epitaxial layer.

    摘要翻译： 一种包括肖特基器件，边缘端接结构，非肖特基半导体器件及其组合的半导体部件和制造半导体部件的方法。 半导体材料包括设置在半导体衬底上的第一外延层和设置在第一外延层上的第二外延层。 第二外延层具有比半导体衬底更高的电阻率。 由第二外延层制造肖特基器件和非肖特基半导体器件。 根据另一实施例，半导体材料包括设置在半导体衬底上的外延层。 外延层具有比半导体衬底更高的电阻率。 在外延层中形成掺杂区域。 由外延层制造肖特基器件和非肖特基半导体器件。

    SEMICONDUCTOR DEVICE HAVING REDUCED GATE CHARGE AND REDUCED ON RESISTANCE AND METHOD
    52.
    发明申请
    SEMICONDUCTOR DEVICE HAVING REDUCED GATE CHARGE AND REDUCED ON RESISTANCE AND METHOD 有权
    具有降低栅极电荷并降低电阻和方法的半导体器件

    公开(公告)号：US20070117305A1

    公开(公告)日：2007-05-24

    申请号：US11624560

    申请日：2007-01-18

    申请人： Prasad Venkatraman ,  Irene Wan

    发明人： Prasad Venkatraman ,  Irene Wan

    IPC分类号： H01L21/8238 ,  H01L29/80

    CPC分类号： H01L29/7802 ,  H01L27/098 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42372

    摘要： In one embodiment, a semiconductor device comprises a semiconductor material having a first conductivity type with a body region of a second conductivity type disposed in the semiconductor material. The body region is adjacent a JFET region. A source region of the first conductivity type is disposed in the body region. A gate layer is disposed over the semiconductor material and has a first opening over the JFET region and a second opening over the body region.

    摘要翻译： 在一个实施例中，半导体器件包括具有第一导电类型的半导体材料，其具有布置在半导体材料中的第二导电类型的体区。 身体区域与JFET区域相邻。 第一导电类型的源极区域设置在身体区域中。 栅极层设置在半导体材料之上，并且在JFET区域上方具有第一开口，并且在身体区域上具有第二开口。

    Trench MOSFET with increased channel density
    54.
    发明授权
    Trench MOSFET with increased channel density 有权
    沟道MOSFET增加通道密度

    公开(公告)号：US06987040B2

    公开(公告)日：2006-01-17

    申请号：US10950754

    申请日：2004-09-27

    申请人： Prasad Venkatraman

    发明人： Prasad Venkatraman

    IPC分类号： H01L21/331 ,  H01L21/8238 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L21/823487 ,  H01L29/0696 ,  H01L29/456 ,  Y10S257/923

    摘要： A MOSFET device (50) has a trench (60) extending from a major surface (56) of the device (50). Within the trench (60), a gate structure (62) is formed where the top surface (64) is below the major surface (56). Source regions (66, 68) are formed along a vertical wall (84) inside of the trench (60). The source regions (66, 68) have a horizontal component along the major surface (56) and a vertical component extending the vertical wall (84). The majority of the source regions (66, 68) are formed along the vertical wall (84) within the trench (60). A typical aspect ratio of the vertical length of the source regions (66, 68) to the horizontal width is greater than 3:1. An Inter-layer dielectric (ILD) layer (74) is formed on the gate structure (62) within the trench (60) below the major surface (56). A metal electrode layer (82) is formed above the major surface (56) where a portion is formed inside the trench (60) making source contact to the source regions (66, 68) inside the trench (60) along the vertical wall (84) of the trench (60).

    摘要翻译： MOSFET器件（50）具有从器件（50）的主表面（56）延伸的沟槽（60）。 在沟槽（60）内，形成栅极结构（62），其中顶表面（64）位于主表面（56）的下方。 源区域（66,68）沿着沟槽（60）内的垂直壁（84）形成。 源区域（66,68）沿着主表面（56）具有水平分量，并且垂直分量延伸垂直壁（84）。 大部分源极区域（66,68）沿沟槽（60）内的垂直壁（84）形成。 源极区域（66,68）的垂直长度与水平宽度的典型纵横比大于3:1。 在主表面（56）下方的沟槽（60）内的栅极结构（62）上形成层间介电层（ILD）层74。 在主表面（56）的上方形成有金属电极层（82），其中形成在沟槽（60）内部的部分，使源极沿垂直壁（...）与沟槽（60）内的源极区域（66,68）接触 84）。

    Low cost method of providing a semiconductor device having a high channel density
    55.
    发明授权
    Low cost method of providing a semiconductor device having a high channel density 有权
    提供具有高通道密度的半导体器件的低成本方法

    公开(公告)号：US06852634B2

    公开(公告)日：2005-02-08

    申请号：US10184187

    申请日：2002-06-27

    申请人： Prasad Venkatraman

    发明人： Prasad Venkatraman

    IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/302

    CPC分类号： H01L21/28512 ,  H01L21/823487

    摘要： A method of making a semiconductor device 10 by forming a first dielectric layer 140 on a substrate, etching through the first dielectric layer to form a trench 150 having a channel region 135 on a sidewall 160 of the trench, and laterally removing a portion of the first dielectric layer adjacent to the sidewall of the trench above the channel region for defining a source region 280 of the semiconductor device.

    摘要翻译： 一种通过在衬底上形成第一电介质层140来制造半导体器件10的方法，通过第一介电层蚀刻以形成在沟槽的侧壁160上具有沟道区域135的沟槽150，并横向移除 第一电介质层，与沟道区域上方的沟槽的侧壁相邻，用于限定半导体器件的源极区域280。

    Method of making a power switching trench MOSFET having aligned source regions
    56.
    发明授权
    Method of making a power switching trench MOSFET having aligned source regions 失效
    制造具有对准的源极区的功率开关沟槽MOSFET的方法

    公开(公告)号：US5897343A

    公开(公告)日：1999-04-27

    申请号：US50164

    申请日：1998-03-30

    申请人： Leo Mathew ,  Keith G. Kamekona ,  Huy Trong Tran ,  Prasad Venkatraman ,  Jeffrey Pearse ,  Bich-Yen Nguyen

    发明人： Leo Mathew ,  Keith G. Kamekona ,  Huy Trong Tran ,  Prasad Venkatraman ,  Jeffrey Pearse ,  Bich-Yen Nguyen

    IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L21/332

    CPC分类号： H01L29/7813 ,  H01L29/0696

    摘要： A trench power switching transistor (10) is fabricated having sub-micron features on a body layer (26) without using sub-micron lithography. An opening in a field oxide layer (28) defines an area for implanting a source region (30) in the body layer (26) that is self-aligned to a first edge (28A) and a second edge (28B) of the field oxide layer (28). Sidewall spacers (32) are formed in accordance with the first and second edges (28A and 28B) of the field oxide layer (28). A trench is aligned to the sidewall spacers (32) and formed centered within the source region (30). An implant layer (42) formed between sections of the power switching transistor (10) is aligned to the sidewall spacers (32) at the first and second edges (28A and 28B).

    摘要翻译： 在不使用亚微米光刻的情况下，在主体层（26）上制造具有亚微米特征的沟槽功率开关晶体管（10）。 场氧化物层（28）中的开口限定用于将源区域（30）注入到主体层（26）中的区域，所述源区域（30）自对准到场的第一边缘（28A）和第二边缘（28B） 氧化物层（28）。 侧壁间隔件（32）根据场氧化物层（28）的第一和第二边缘（28A和28B）形成。 沟槽与侧壁间隔件（32）对准，并形成在源区域（30）的中心。 形成在功率开关晶体管（10）的部分之间的注入层（42）在第一和第二边缘（28A和28B）处与侧壁间隔件（32）对准。

    SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
    57.
    发明申请
    SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE 有权
    半导体元件及其制造方法

    公开(公告)号：US20110266613A1

    公开(公告)日：2011-11-03

    申请号：US12771869

    申请日：2010-04-30

    申请人： Prasad Venkatraman ,  Zia Hossain ,  Kirk K. Huang

    发明人： Prasad Venkatraman ,  Zia Hossain ,  Kirk K. Huang

    IPC分类号： H01L27/06 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/0638 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

    摘要： A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shield electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shield electrodes. A gate electrode in at least one of the trenches is connected to at least one shield electrode in the trenches.

    摘要翻译： 包括栅电极和屏蔽电极的半导体部件和制造半导体部件的方法。 半导体材料具有器件区域，栅极接触区域，端接区域和漏极接触区域。 在器件区域中形成一个或多个器件沟槽，并且在边缘端接区域中形成一个或多个端接沟槽。 屏蔽电极形成在与其底板相邻的器件沟槽的部分中。 栅极电介质材料形成在器件区域中的沟槽的侧壁上，并且栅电极形成在屏蔽电极之上并与屏蔽电极电隔离。 至少一个沟槽中的栅电极连接到沟槽中的至少一个屏蔽电极。