公开(公告)号：US07482221B2

公开(公告)日：2009-01-27

申请号：US11203927

申请日：2005-08-15

申请人： Klaus Muemmler ,  Stefan Tegen ,  Peter Baars ,  Joern Regul

发明人： Klaus Muemmler ,  Stefan Tegen ,  Peter Baars ,  Joern Regul

IPC分类号： H01L21/8242

CPC分类号： H01L28/90 ,  H01L27/105 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897

摘要： The invention relates to a method of forming a memory device comprising a memory cell array and a peripheral portion. When forming the capacitors in the memory cell array, a sacrificial layer is deposited which is usually made of silicon dioxide and which is used for defining the storage electrode above the substrate surface. The sacrificial layer is removed selectively from the array portion while being maintained in the peripheral portion. This is achieved by providing an array separation trench which acts as a lateral etch stop.

摘要翻译： 本发明涉及一种形成包括存储单元阵列和周边部分的存储器件的方法。 当在存储单元阵列中形成电容器时，沉积牺牲层，该牺牲层通常由二氧化硅制成，并且用于在衬底表面上限定存储电极。 牺牲层在保持在周边部分的同时从阵列部分选择性地移除。 这通过提供用作横向蚀刻停止的阵列分离沟槽来实现。

公开(公告)号：US20080128773A1

公开(公告)日：2008-06-05

申请号：US11633090

申请日：2006-12-04

申请人： Peter Moll ,  Peter Baars ,  Till Schloesser ,  Rolf Weis ,  Klaus Muemmler

发明人： Peter Moll ,  Peter Baars ,  Till Schloesser ,  Rolf Weis ,  Klaus Muemmler

IPC分类号： H01L27/108

CPC分类号： H01L28/90 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897

摘要： A storage capacitor includes a first capacitor portion and a second capacitor portion, the second capacitor portion being disposed above the first capacitor portion, thereby defining a first direction. The first and the second portions each include a hollow body made of a conductive material, respectively, thereby forming a first capacitor electrode. An upper diameter of each of the hollow bodies is larger than a lower diameter of the hollow body, the diameter being measured perpendicularly with respect to the first direction. The storage capacitor also includes a second capacitor electrode and a dielectric material disposed between the first and the second capacitor electrodes. The storage capacitor also includes an insulating material disposed outside the hollow bodies, and a layer of an insulating material. A lower side of the insulating layer is disposed at a height of an upper side of the first capacitor portion.

摘要翻译： 存储电容器包括第一电容器部分和第二电容器部分，第二电容器部分设置在第一电容器部分上方，从而限定第一方向。 第一和第二部分分别包括由导电材料制成的中空体，从而形成第一电容器电极。 每个中空体的上直径大于中空体的下直径，其直径相对于第一方向垂直地被测量。 存储电容器还包括设置在第一和第二电容器电极之间的第二电容器电极和介电材料。 存储电容器还包括设置在中空体外部的绝缘材料和绝缘材料层。 绝缘层的下侧设置在第一电容器部分的上侧的高度处。

公开(公告)号：US07374992B2

公开(公告)日：2008-05-20

申请号：US11443602

申请日：2006-05-31

申请人： Peter Baars ,  Klaus Muemmler ,  Matthias Goldbach

发明人： Peter Baars ,  Klaus Muemmler ,  Matthias Goldbach

IPC分类号： H01L21/8234

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/10811 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

摘要： The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; forming a first contact hole between two neighboring gate stacks in said memory cell region; depositing a first protective layer over said memory cell region and peripheral device region; exposing said cap of said at least one gate stack in said peripheral device region; modifying said exposed cap of said at least one gate stack in said peripheral device region in a process step wherein said first protective layer acts as a mask in said memory cell region; forming a second protective layer over said modified cap in said peripheral device region; partly removing said first and second protective layer in order to bring said first and second protective layer to about a same upper level; removing said first protective layer from said first contact hole; forming at least one another contact hole in said peripheral device region, said at least one another contact hole exposing another contact area which is located either adjacent to said gate stack or in said gate stack in said peripheral device region; and filling said contact hole and said at least one another contact hole with a respective contact plug.

摘要翻译： 本发明提供了一种用于集成半导体结构的制造方法，包括以下步骤：提供在存储单元区域中具有多个栅极堆叠的半导体衬底和在外围器件区域中的至少一个栅极堆叠; 在所述存储单元区域中的所述多个栅极堆叠上并在所述外围设备区域中的所述至少一个栅极堆叠上形成由一层或多层盖材料构成的盖; 在所述存储单元区域中的两个相邻栅极堆叠之间形成第一接触孔; 在所述存储单元区域和外围设备区域上沉积第一保护层; 将所述至少一个栅极堆叠的所述盖暴露在所述外围设备区域中; 在处理步骤中修改所述外围设备区域中的所述至少一个栅极堆叠的所述暴露的盖，其中所述第一保护层用作所述存储单元区域中的掩模; 在所述外围设备区域中的所述修改的盖上形成第二保护层; 部分地去除所述第一和第二保护层，以便使所述第一和第二保护层大致相同的上层; 从所述第一接触孔去除所述第一保护层; 在所述外围设备区域中形成至少另一个接触孔，所述至少另一个接触孔暴露位于所述外围设备区域中与所述栅极堆叠相邻或所述栅极叠层中的另一个接触区域; 以及用相应的接触插塞填充所述接触孔和所述至少另一个接触孔。

公开(公告)号：US20070155119A1

公开(公告)日：2007-07-05

申请号：US11321450

申请日：2005-12-30

申请人： Klaus Muemmler ,  Peter Baars ,  Stefan Tegen

发明人： Klaus Muemmler ,  Peter Baars ,  Stefan Tegen

IPC分类号： H01L21/76

CPC分类号： H01L29/66621 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66545 ,  H01L29/66553

摘要： Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A protection liner covers the semiconductor fin and the trench isolations in a bottom portion of the gate groove and the pockets. An insulator collar is formed in the exposed upper sections of the gate groove and the pockets, wherein a lower edge of the insulator collar corresponds to a lower edge of source/drain regions formed within the semiconductor fin. The protection liner is removed. The bottom portion of the gate groove and the pockets are covered with a gate dielectric and a buried gate conductor layer. The protection liner avoids residuals of polycrystalline silicon between the active area in the semiconductor fin and the insulator collar.

摘要翻译： 具有拐角栅极器件的凹槽通道阵列晶体管（RCAT）的制造包括在包括栅极沟槽的半导体鳍片之间形成凹穴以及沿着半导体鳍片的长边延伸的相邻浅沟槽隔离件。 保护衬套覆盖半导体鳍片和栅极沟槽和凹穴的底部中的沟槽隔离。 绝缘体套环形成在门槽和凹穴的暴露的上部中，其中绝缘体环的下边缘对应于形成在半导体鳍内的源/漏区的下边缘。 保护衬垫被取下。 栅极槽和凹穴的底部被栅极电介质和掩埋栅极导体层覆盖。 保护衬垫避免了半导体鳍片的有源区域和绝缘体套环之间的多晶硅残留。

公开(公告)号：US08927407B2

公开(公告)日：2015-01-06

申请号：US13354739

申请日：2012-01-20

申请人： Peter Baars ,  Andy Wei ,  Erik Geiss ,  Martin Mazur

发明人： Peter Baars ,  Andy Wei ,  Erik Geiss ,  Martin Mazur

IPC分类号： H01L21/28

CPC分类号： H01L21/76897 ,  H01L29/66545

摘要： Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.

摘要翻译： 本文公开了一种形成用于半导体器件的自对准接触件的方法。 在一个示例中，该方法包括在半导体衬底之上形成多个间隔开的牺牲栅电极，其中每个栅电极具有位于栅电极上的栅极帽层，并执行至少一个蚀刻工艺以限定自身 在多个间隔开的牺牲栅电极之间的对准接触开口。 该方法还包括去除栅极盖层，从而暴露每个牺牲栅电极的上表面，在所述自对准接触开口中沉积至少一层导电材料，并去除至少一层导电材料的部分 其定位在自对准接触开口的外侧，从而限定位于自对准接触开口中的自对准接触件的至少一部分。

公开(公告)号：US08765586B2

公开(公告)日：2014-07-01

申请号：US13331842

申请日：2011-12-20

申请人： Clemens Fitz ,  Peter Baars ,  Markus Lenski

发明人： Clemens Fitz ,  Peter Baars ,  Markus Lenski

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76814 ,  H01L29/41783 ,  H01L29/66545

摘要： Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer.

摘要翻译： 本文公开了在半导体器件上形成金属硅化物区域的各种方法。 在一个示例中，该方法包括在半导体衬底之上形成牺牲栅极结构，在形成金属硅化物区域之后，执行选择性金属硅化物形成工艺以形成在衬底中或上方形成的源极/漏极区域中的金属硅化物区域， 牺牲栅极结构以限定栅极开口并在栅极开口中形成替代栅极结构，所述替换栅极结构由至少一个金属层组成。

公开(公告)号：US08647938B1

公开(公告)日：2014-02-11

申请号：US13571190

申请日：2012-08-09

申请人： Peter Baars ,  Matthias Goldbach

发明人： Peter Baars ,  Matthias Goldbach

IPC分类号： H01L21/336

CPC分类号： H01L27/1104 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/66545

摘要： SRAM ICs and methods for their fabrication are provided. One method includes depositing photoresist on a first oxide layer overlying a silicon substrate, forming a pattern of locations, using said photoresist, for the formation of two inverters, each having a pull up transistor, a pull down transistor, and a pass gate transistor on said oxide layer. The method involves anisotropically etching U-shaped channels in the oxide layer corresponding to pattern, and thereafter isotropically etching U-shaped channels in the silicon layer to form saddle-shaped fins in the silicon. A second oxide layer is deposited over the saddle-shaped fins, and a first metal layer is deposited over the second oxide layer. A contact metal layer is formed over the first metal layer and planarized to form local interconnections coupling the gate electrodes of one inverter to a node between the pull up and pull down transistors of the other inverter and to a source/drain of one of the pass gate transistors.

摘要翻译： 提供SRAM IC及其制造方法。 一种方法包括在覆盖硅衬底的第一氧化物层上沉积光致抗蚀剂，使用所述光致抗蚀剂形成位置图案，以形成两个反相器，每个具有上拉晶体管，下拉晶体管和通过栅极晶体管 所述氧化物层。 该方法涉及各向异性蚀刻对应于图案的氧化物层中的U形通道，然后各向同性蚀刻硅层中的U形通道，以在硅中形成鞍形翅片。 在鞍形翅片上沉积第二氧化物层，并且在第二氧化物层上沉积第一金属层。 接触金属层形成在第一金属层之上并被平坦化以形成将一个反相器的栅电极耦合到另一个反相器的上拉和下拉晶体管之间的节点的局部互连，以及一个通过的一个的源极/漏极 栅极晶体管。

公开(公告)号：US20130193516A1

公开(公告)日：2013-08-01

申请号：US13359242

申请日：2012-01-26

申请人： Matthias Goldbach ,  Peter Baars

发明人： Matthias Goldbach ,  Peter Baars

IPC分类号： H01L27/11 ,  H01L21/762 ,  H01L21/336

CPC分类号： H01L21/76224 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/0207 ,  H01L27/1104

摘要： SRAM ICs and methods for their fabrication are provided. One method includes forming dummy gate electrodes overlying a semiconductor substrate and defining locations of gate electrodes for two cross coupled inverters and two pass gate transistors. A first insulating layer is deposited overlying the dummy gate electrodes and gaps between the dummy gate electrodes are filled with a second insulating layer. The second insulating layer is etched to form inter-gate openings exposing portions of the substrate. The first insulating layer is etched to reduce the thickness of selected locations thereof, and the dummy gate electrodes are removed. A gate electrode metal is deposited and planarized to form gate electrodes and local interconnections coupling the gate electrodes of one inverter to a node between the pull up and pull down transistors of the other inverter and to a source/drain of one of the pass gate transistors.

摘要翻译： 提供SRAM IC及其制造方法。 一种方法包括形成覆盖在半导体衬底上的虚拟栅电极并且限定用于两个交叉耦合的反相器和两个通过栅极晶体管的栅电极的位置。 第一绝缘层沉积在虚拟栅电极的上方，并且虚设栅电极之间的间隙填充有第二绝缘层。 蚀刻第二绝缘层以形成露出衬底的部分的栅极间开口。 蚀刻第一绝缘层以减小其选定位置的厚度，并且去除伪栅极电极。 栅极电极金属被沉积并平坦化以形成将一个反相器的栅电极耦合到另一个反相器的上拉和下拉晶体管之间的节点的栅电极和局部互连，以及一个通栅晶体管之一的源极/漏极 。

公开(公告)号：US20130189833A1

公开(公告)日：2013-07-25

申请号：US13354739

申请日：2012-01-20

申请人： Peter Baars ,  Andy Wei ,  Erik Geiss ,  Martin Mazur

发明人： Peter Baars ,  Andy Wei ,  Erik Geiss ,  Martin Mazur

IPC分类号： H01L21/28

CPC分类号： H01L21/76897 ,  H01L29/66545

摘要： Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.

摘要翻译： 本文公开了一种形成用于半导体器件的自对准接触件的方法。 在一个示例中，该方法包括在半导体衬底之上形成多个间隔开的牺牲栅电极，其中每个栅电极具有位于栅电极上的栅极帽层，并执行至少一个蚀刻工艺以限定自身 在多个间隔开的牺牲栅电极之间的对准接触开口。 该方法还包括去除栅极盖层，从而暴露每个牺牲栅电极的上表面，在所述自对准接触开口中沉积至少一层导电材料，并去除至少一层导电材料的部分 其定位在自对准接触开口的外侧，从而限定位于自对准接触开口中的自对准接触件的至少一部分。

公开(公告)号：US08455960B2

公开(公告)日：2013-06-04

申请号：US13185112

申请日：2011-07-18

申请人： Frank Jakubowski ,  Peter Baars ,  Till Schloesser

发明人： Frank Jakubowski ,  Peter Baars ,  Till Schloesser

IPC分类号： H01L29/00

CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/7833

摘要： Semiconductor devices are formed with a silicide interface between the work function layer and polycrystalline silicon. Embodiments include forming a high-k/metal gate stack by: forming a high-k dielectric layer on a substrate, forming a work function metal layer on the high-k dielectric layer, forming a silicide on the work function metal layer, and forming a poly Si layer on the silicide. Embodiments include forming the silicide by: forming a reactive metal layer in situ on the work function layer, forming an a-Si layer in situ on the entire upper surface of the reactive metal layer, and annealing concurrently with forming the poly Si Layer.

摘要翻译： 半导体器件在功函数层与多晶硅之间形成硅化物界面。 实施例包括通过以下方式形成高k /金属栅极堆叠：在衬底上形成高k电介质层，在高k电介质层上形成功函数金属层，在功函数金属层上形成硅化物，以及形成 硅化物上的多晶硅层。 实施例包括：通过在功函数层上原位形成反应性金属层，在反应性金属层的整个上表面上原位形成a-Si层，并与形成多晶硅层同时进行退火来形成硅化物。