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    Methods of Forming Metal Silicide Regions on Semiconductor Devices
    1.
    发明申请
    Methods of Forming Metal Silicide Regions on Semiconductor Devices 有权
    在半导体器件上形成金属硅化物区域的方法

    公开(公告)号：US20130157450A1

    公开(公告)日：2013-06-20

    申请号：US13331842

    申请日：2011-12-20

    申请人： Clemens Fitz ,  Peter Baars ,  Markus Lenski

    发明人： Clemens Fitz ,  Peter Baars ,  Markus Lenski

    IPC分类号： H01L21/283

    CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76814 ,  H01L29/41783 ,  H01L29/66545

    摘要： Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer.

    摘要翻译： 本文公开了在半导体器件上形成金属硅化物区域的各种方法。 在一个示例中，该方法包括在半导体衬底之上形成牺牲栅极结构，在形成金属硅化物区域之后，执行选择性金属硅化物形成工艺以形成在衬底中或上方形成的源极/漏极区域中的金属硅化物区域， 牺牲栅极结构以限定栅极开口并在栅极开口中形成替代栅极结构，所述替换栅极结构由至少一个金属层组成。

    Methods of forming metal silicide regions on semiconductor devices
    2.
    发明授权
    Methods of forming metal silicide regions on semiconductor devices 有权
    在半导体器件上形成金属硅化物区域的方法

    公开(公告)号：US08765586B2

    公开(公告)日：2014-07-01

    申请号：US13331842

    申请日：2011-12-20

    申请人： Clemens Fitz ,  Peter Baars ,  Markus Lenski

    发明人： Clemens Fitz ,  Peter Baars ,  Markus Lenski

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76814 ,  H01L29/41783 ,  H01L29/66545

    摘要： Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer.

    摘要翻译： 本文公开了在半导体器件上形成金属硅化物区域的各种方法。 在一个示例中，该方法包括在半导体衬底之上形成牺牲栅极结构，在形成金属硅化物区域之后，执行选择性金属硅化物形成工艺以形成在衬底中或上方形成的源极/漏极区域中的金属硅化物区域， 牺牲栅极结构以限定栅极开口并在栅极开口中形成替代栅极结构，所述替换栅极结构由至少一个金属层组成。

    Methods for fabricating a CMOS integrated circuit having a dual stress layer (DSL)
    3.
    发明授权
    Methods for fabricating a CMOS integrated circuit having a dual stress layer (DSL) 有权
    制造具有双重应力层（DSL）的CMOS集成电路的方法

    公开(公告)号：US08293605B2

    公开(公告)日：2012-10-23

    申请号：US13034902

    申请日：2011-02-25

    申请人： Peter Baars ,  Marco Lepper ,  Clemens Fitz

    发明人： Peter Baars ,  Marco Lepper ,  Clemens Fitz

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L21/3105 ,  H01L21/823814 ,  H01L21/823864

    摘要： Methods are provided for fabricating a CMOS integrated circuit having a dual stress layer without NiSi hole formation. One method includes depositing a tensile stress layer overlying a semiconductor substrate. A portion of the tensile stress layer is removed, leaving a remaining portion, before applying a curing radiation. A curing radiation is then applied to the remaining portion; and a compressive stress layer is deposited overlying the semiconductor substrate and the remaining portion.

    摘要翻译： 提供了用于制造具有不具有NiSi孔形成的双应力层的CMOS集成电路的方法。 一种方法包括沉积覆盖半导体衬底的拉伸应力层。 在施加固化辐射之前，去除一部分拉伸应力层，留下剩余部分。 然后将固化辐射施加到剩余部分; 并且沉积覆盖半导体衬底和剩余部分的压应力层。

    METHODS FOR FABRICATING A CMOS INTEGRATED CIRCUIT HAVING A DUAL STRESS LAYER (DSL)
    5.
    发明申请
    METHODS FOR FABRICATING A CMOS INTEGRATED CIRCUIT HAVING A DUAL STRESS LAYER (DSL) 有权
    用于制造具有双应力层（DSL）的CMOS集成电路的方法

    公开(公告)号：US20120220086A1

    公开(公告)日：2012-08-30

    申请号：US13034902

    申请日：2011-02-25

    申请人： Peter Baars ,  Marco Lepper ,  Clemens Fitz

    发明人： Peter Baars ,  Marco Lepper ,  Clemens Fitz

    IPC分类号： H01L21/8238 ,  H01L21/30

    CPC分类号： H01L21/823807 ,  H01L21/3105 ,  H01L21/823814 ,  H01L21/823864

    摘要： Methods are provided for fabricating a CMOS integrated circuit having a dual stress layer without NiSi hole formation. One method includes depositing a tensile stress layer overlying a semiconductor substrate. A portion of the tensile stress layer is removed, leaving a remaining portion, before applying a curing radiation. A curing radiation is then applied to the remaining portion; and a compressive stress layer is deposited overlying the semiconductor substrate and the remaining portion.

    摘要翻译： 提供了用于制造具有不具有NiSi孔形成的双应力层的CMOS集成电路的方法。 一种方法包括沉积覆盖半导体衬底的拉伸应力层。 在施加固化辐射之前，去除一部分拉伸应力层，留下剩余部分。 然后将固化辐射施加到剩余部分; 并且沉积覆盖半导体衬底和剩余部分的压应力层。

    Integrated circuits that include deep trench capacitors and methods for their fabrication
    6.
    发明授权
    Integrated circuits that include deep trench capacitors and methods for their fabrication 有权
    集成电路包括深沟槽电容器及其制造方法

    公开(公告)号：US08853810B2

    公开(公告)日：2014-10-07

    申请号：US13218262

    申请日：2011-08-25

    申请人： Peter Baars ,  Till Schloesser

    发明人： Peter Baars ,  Till Schloesser

    IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L27/12 ,  H01L21/84 ,  H01L27/02 ,  H01L49/02

    CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91

    摘要： Methods are provided for fabricating an integrated circuit that includes a deep trench capacitor. One method includes fabricating a plurality of transistors on a semiconductor substrate, the plurality of transistors each including gate structures, source and drain regions, and silicide contacts to the source and drain regions. A trench is then etched into the semiconductor substrate in proximity to the drain region of a selected transistor. The trench is filled with a layer of metal in contact with the semiconductor substrate, a layer of dielectric material overlying the layer of metal, and a second metal overlying the layer of dielectric material. A metal contact is then formed coupling the second metal to the silicide contact on the drain region of the selected transistor. A bit line is formed contacting the source region of the selected transistor and a word line is formed contacting the gate structure of the transistor.

    摘要翻译： 提供了用于制造包括深沟槽电容器的集成电路的方法。 一种方法包括在半导体衬底上制造多个晶体管，所述多个晶体管各自包括栅极结构，源极和漏极区以及到源极和漏极区的硅化物接触。 然后在所选择的晶体管的漏极区域附近将沟槽蚀刻到半导体衬底中。 沟槽填充有与半导体衬底接触的金属层，覆盖金属层的电介质材料层和覆盖在介电材料层上的第二金属。 然后形成金属接触，将第二金属耦合到所选晶体管的漏极区上的硅化物接触。 与所选择的晶体管的源极区域接触的位线形成为与晶体管的栅极结构接触的字线。

    Method of removing gate cap materials while protecting active area
    9.
    发明授权
    Method of removing gate cap materials while protecting active area 有权
    在保护有源区域的同时去除栅极盖材料的方法

    公开(公告)号：US08697557B2

    公开(公告)日：2014-04-15

    申请号：US13154521

    申请日：2011-06-07

    申请人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski

    发明人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski

    IPC分类号： H01L29/78

    CPC分类号： H01L29/6659 ,  H01L21/31053 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

    摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming a gate electrode structure above a semiconducting substrate, wherein the gate electrode structure includes a gate insulation layer, a gate electrode, a first sidewall spacer positioned proximate the gate electrode, and a gate cap layer, and forming an etch stop layer above the gate cap layer and above the substrate proximate the gate electrode structure. The method further includes forming a layer of spacer material above the etch stop layer, and performing at least one first planarization process to remove the portion of said layer of spacer material positioned above the gate electrode, the portion of the etch stop layer positioned above the gate electrode and the gate cap layer.

    摘要翻译： 本文公开了形成半导体器件的方法。 在一个示例中，该方法包括在半导体衬底之上形成栅电极结构，其中栅电极结构包括栅极绝缘层，栅极电极，靠近栅电极定位的第一侧壁隔离物和栅极盖层，以及形成 栅极覆盖层上方的蚀刻停止层，以及靠近栅电极结构的衬底上方的蚀刻停止层。 该方法还包括在蚀刻停止层上方形成间隔物材料层，以及执行至少一个第一平面化处理以去除位于栅极电极上方的所述隔离层材料层的部分，所述蚀刻停止层的部分位于 栅电极和栅极帽层。