公开(公告)号：US10511397B2

公开(公告)日：2019-12-17

申请号：US15878790

申请日：2018-01-24

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Sharon Graif ,  Lalan Jee Mishra

IPC: H04J3/02 ,  G06F3/16 ,  G06F13/42 ,  H04L12/40 ,  H04B1/38

Abstract: Systems and methods for providing virtual general purpose input/output (GPIO) (VGI) over a time division multiplex (TDM) bus are disclosed. While a SOUNDWIRE bus is particularly contemplated, other TDM buses may also be used to provide the benefits outlined herein. In particular, raw GPIO signals are placed into time slots on a TDM bus without requiring additional overhead or packaging. This arrangement allows all drops on a multi-drop bus to receive the GPIO signals substantially concurrently with latency measured in less than a frame period.

公开(公告)号：US10474622B1

公开(公告)日：2019-11-12

申请号：US16036273

申请日：2018-07-16

Applicant: QUALCOMM Incorporated

Inventor： Richard Dominic Wietfeldt ,  Lalan Jee Mishra

IPC: G06F13/42 ,  G06F13/40

Abstract: Systems, methods, and apparatus for improving bus latency are described. A method performed at a transmitting device includes receiving a datagram to be transmitted from the transmitting device to a receiving device, determining whether a first serial bus coupling the transmitting device to the receiving device is available to transmit the datagram, determining whether a second serial bus coupling the transmitting device to the receiving device is available to transmit the datagram, transmitting the datagram over the first serial bus when the first serial bus is available, and transmitting the datagram over the second serial bus when the second serial bus is available and when the first serial bus is unavailable. The datagram is associated with a latency budget. The first or second serial bus may be available to transmit the datagram when active and likely to transmit the datagram within a time limit defined by the latency budget.

公开(公告)号：US20180267916A1

公开(公告)日：2018-09-20

申请号：US15989067

申请日：2018-05-24

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F13/362 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/362 ,  G06F13/4068 ,  G06F13/4282 ,  G06F13/4291

Abstract: A modified serial peripheral interface (SPI) is provided in each of a master device and a plurality of slave devices that does not use a slave select line. The master device may thus engage in full-duplex serial communication with each slave device through an SPI MOSI line, an SPI MISO line, and an SPI clock line.

公开(公告)号：US20180173665A1

公开(公告)日：2018-06-21

申请号：US15382102

申请日：2016-12-16

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F13/364 ,  G06F13/404

Abstract: Systems, methods, and apparatus are described that enable communication of in-band reset signals over a serial bus. A method performed at a slave device coupled to the serial bus includes configuring a reset controller to operate in one of plural modes, identifying a first reset pattern in signaling received from a multi-wire serial bus, complying with one or more transmissions defined by the protocol, asserting a reset input of a processing circuit in the slave device responsive to an identification of the first reset pattern when the reset controller is operated in a first mode, and ignoring the first reset pattern when the reset controller is operated in a second mode. The signaling received from the multi-wire serial bus may include one or more transmissions defined by a protocol used on the multi-wire serial bus. The reset controller may operate autonomously from the processing circuit in the first mode.

公开(公告)号：US09747244B2

公开(公告)日：2017-08-29

申请号：US14540366

申请日：2014-11-13

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Mohit Kishore Prasad

IPC: G06F13/12 ,  G06F13/42 ,  G06F9/455

CPC classification number: G06F13/4221 ,  G06F9/45533 ,  G06F13/4273

Abstract: A virtual GPIO architecture for an integrated circuit is provided that both serializesvirtual GPIO signals and deserializes virtual GPIO signals without the need for an external clock.

公开(公告)号：US20170199832A1

公开(公告)日：2017-07-13

申请号：US14994242

申请日：2016-01-13

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F13/364 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F13/404 ,  G06F13/4282 ,  G06F13/4291 ,  H04B1/0458 ,  H04B1/18 ,  H04L12/40019 ,  H04L12/4013 ,  Y02D10/14 ,  Y02D10/151

Abstract: Signaling protocols for radio frequency front-end control interface (RFFE) buses are disclosed. In an exemplary aspect, the RFFE protocol is modified to provide addresses that are shorter than the normal four bits allocated by the RFFE protocol. By allocating fewer bits to an address, frames sent across an RFFE bus are shorter, and thus, bus turnaround time is improved, which reduces overall latency. Further, it is possible that shorter messages may provide incremental power savings. In a further exemplary aspect, different portions of a frame are transmitted using different data rates. In particular, a bus management portion may be sent using a single data rate (SDR), and a payload portion may be sent using a double data rate (DDR). The net effect of using the DDR on the payload portion is to reduce bus turnaround time, and thus, reduce latency.

公开(公告)号：US09684487B2

公开(公告)日：2017-06-20

申请号：US14631078

申请日：2015-02-25

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  George Alan Wiley

IPC: G06F13/00 ,  G06F5/16 ,  G06F13/40 ,  G06F13/16 ,  G06F1/12 ,  G06F5/06 ,  G06F13/38

CPC classification number: G06F5/16 ,  G06F1/12 ,  G06F5/065 ,  G06F13/1673 ,  G06F13/385 ,  G06F13/4022

Abstract: A line multiplexed UART interface is provided that multiplexes a UART transmit and CTS functions on a transmit pin and that multiplexes a UART receive and RTS functions on a receive pin. In this fashion, the conventional need for an additional RTS pin and an additional CTS pin is obviated such that the line multiplexed UART interface uses just the transmit pin and the receive pin.

公开(公告)号：US09619427B2

公开(公告)日：2017-04-11

申请号：US14533431

申请日：2014-11-05

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Mohit Kishore Prasad ,  James Lionel Panian

IPC: G06F9/44 ,  G06F13/42 ,  G06F13/40 ,  G06F15/76 ,  G06F9/54

CPC classification number: G06F13/4252 ,  G06F9/4498 ,  G06F9/546 ,  G06F13/4022 ,  G06F13/4068 ,  G06F15/76 ,  G06F2015/761

Abstract: A finite state machine is provided that both serializes virtual GPIO signals and messaging signals and that deserializer virtual GPIO signals and the messaging signals. The finite state machine frames the serialized virtual GPIO signals and messaging signals into frames each demarcated by a start bit and an end bit.

公开(公告)号：US20160285968A1

公开(公告)日：2016-09-29

申请号：US15077841

申请日：2016-03-22

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  James Panian ,  Richard Wietfeldt

IPC: H04L29/08 ,  H04L29/12

CPC classification number: H04L67/1091 ,  G06F13/4247 ,  G06F2213/0052 ,  H04L61/2007 ,  H04L61/604

Abstract: An enumeration technique is provided that requires no pre-assignment of addresses to slave devices connected through P2P links to a host device. With regard to any P2P link between devices, one device has a master interface and the remaining device has a slave interface. To distinguish between the master and slave interfaces, a master/slave status bit may be used. Each P2P link has a link ID that may be concatenated with the status bit for a corresponding interface (slave or master) to form a node ID. The host device receives a unique concatenated address from each slave device that represents a concatenation of the node ID for the slave and the node ID for any intervening interfaces between the slave device and the host device. The host device then assigns a unique Cartesian address to each slave device.

Abstract translation: 提供了一种枚举技术，其不需要将通过P2P链接连接到主机设备的从设备的地址预先分配。 关于设备之间的任何P2P链路，一个设备具有主接口，其余设备具有从接口。 为了区分主从接口，可以使用主/从状态位。 每个P2P链路具有可以与相应接口（从属或主机）的状态位连接以形成节点ID的链路ID。 主设备从每个从设备接收代表从设备的节点ID的级联和从设备与主设备之间的任何介入接口的节点ID的唯一的级联地址。 然后，主机设备为每个从设备分配唯一的笛卡尔地址。

公开(公告)号：US20160259702A1

公开(公告)日：2016-09-08

申请号：US15060221

申请日：2016-03-03

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  James Lionel Panian ,  George Alan Wiley ,  Amit Gil

IPC: G06F11/30 ,  G06F15/17 ,  G06F1/32 ,  G06F9/44 ,  G06F15/78

CPC classification number: G06F11/3051 ,  G06F1/3209 ,  G06F1/3278 ,  G06F9/4418 ,  G06F11/3041 ,  G06F15/17 ,  G06F15/7807 ,  Y02D10/157

Abstract: System, methods, and apparatuses are described that facilitate a first device to transmit/retransmit a message to a second device. The first device transmits a first message to the second device. The first device then receives a second message and identifies a hit of the second message indicating an originator of the second message. If the bit indicates the first device as the originator of the second message, then the second message is an echo of the first message, Reception of the echo indicates that the second device is in a sleep state. Accordingly, the first device waits for the second device to wake and retransmits the first message to the second device to ensure that any packets lost during the original transmission of the first message (when the second device was asleep) are now retransmitted while the second device is known to be awake.

Abstract translation: 描述了便于第一设备向第二设备发送/重发消息的系统，方法和设备。 第一设备向第二设备发送第一消息。 然后，第一设备接收第二消息并识别指示第二消息的发起者的第二消息的命中。 如果该比特指示第一个设备作为第二个消息的发起者，则第二个消息是第一个消息的回应，回应的接收表明第二个设备处于睡眠状态。 因此，第一设备等待第二设备唤醒并将第一消息重新发送到第二设备，以确保在第一消息的原始传输期间（当第二设备睡着时）丢失的任何分组现在在第二设备 已知醒来。