公开(公告)号：US20220171721A1

公开(公告)日：2022-06-02

申请号：US17548510

申请日：2021-12-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright ,  John Eric Linstadt ,  Craig Hampel

IPC: G06F13/16 ,  G06F12/0868 ,  G06F12/0888 ,  G11C7/10 ,  G06F3/06 ,  G06F11/10 ,  G06F12/0895 ,  G06F13/28 ,  G11C29/52

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.

公开(公告)号：US11341070B2

公开(公告)日：2022-05-24

申请号：US17100560

申请日：2020-11-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C7/22 ,  G11C29/02 ,  G11C5/02

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

公开(公告)号：US11308009B2

公开(公告)日：2022-04-19

申请号：US16548714

申请日：2019-08-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright

IPC: G06F11/00 ,  G06F13/16 ,  G06F11/07 ,  G06F13/40 ,  G06F11/20 ,  G06F11/16 ,  G06F11/10

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

公开(公告)号：US20210374004A1

公开(公告)日：2021-12-02

申请号：US17354268

申请日：2021-06-22

Applicant: Rambus Inc.

Inventor： Kenneth L. Wright ,  Frederick A. Ware

IPC: G06F11/14 ,  H01L23/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/40 ,  G06F11/00 ,  H01L25/065 ,  H01L25/10

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.

公开(公告)号：US11069392B2

公开(公告)日：2021-07-20

申请号：US17099413

申请日：2020-11-16

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Brent Steven Haukness ,  Kenneth L. Wright ,  Thomas Vogelsang

IPC: G11C11/24 ,  G11C11/403 ,  G11C11/4096 ,  G11C8/08 ,  G11C7/10 ,  G11C7/18 ,  G11C5/02 ,  G11C11/408 ,  G06F12/06 ,  G11C11/406 ,  G11C11/409 ,  G11C11/4097 ,  G11C11/4091

Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.

公开(公告)号：US20210173800A1

公开(公告)日：2021-06-10

申请号：US17100560

申请日：2020-11-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G11C7/10 ,  G11C5/04 ,  G06F13/16

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

公开(公告)号：US20200321048A1

公开(公告)日：2020-10-08

申请号：US16856596

申请日：2020-04-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C7/02 ,  G11C29/52

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US10734064B1

公开(公告)日：2020-08-04

申请号：US15992100

申请日：2018-05-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4091 ,  G06F12/14 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4072 ,  G11C29/38 ,  G11C29/32 ,  G11C29/22 ,  G11C5/04

Abstract: A memory control component has control circuitry and a data interface, the data interface to be coupled, via a plurality of data signaling paths, to a respective plurality of memory dies disposed on a memory module. The control circuitry transmits to the memory module a first configuration value that specifies a memory die quantity N that is permitted to range from a first value corresponding to the quantity of the data signaling paths to at least one value less than the first value. Thereafter, the control circuitry transmits a memory read command to the memory module to enable, in accordance with the first configuration value, a quantity N of the memory dies to output read data and enables the data interface to receive the read data via a respective quantity N of the data signaling paths.

公开(公告)号：US10409742B2

公开(公告)日：2019-09-10

申请号：US15284307

申请日：2016-10-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright

IPC: G06F11/00 ,  G06F13/16 ,  G06F11/07 ,  G06F13/40

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

公开(公告)号：US20190259435A1

公开(公告)日：2019-08-22

申请号：US16344321

申请日：2017-10-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C11/00 ,  G11C14/00 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0895 ,  G11C5/04

Abstract: A memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive nonvolatile memory. Local controller manages communication between the DRAM cache and nonvolatile memory to accommodate disparate access granularities, reduce the requisite number of memory transactions, and minimize the flow of data external to nonvolatile memory components.