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    Load reduced memory module
    51.
    发明授权
    Load reduced memory module 有权

    公开(公告)号：US11317510B2

    公开(公告)日：2022-04-26

    申请号：US17072775

    申请日：2020-10-16

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Suresh Rajan

    IPC: G11C7/10 ,  H05K1/11 ,  G11C11/4093 ,  H05K1/18 ,  G06F15/78 ,  G11C11/408 ,  G06F1/18 ,  G11C5/04 ,  G11C5/06 ,  G06F13/16 ,  G06F13/40

    Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

    High capacity memory system with improved command-address and chip-select signaling mode
    52.
    发明授权
    High capacity memory system with improved command-address and chip-select signaling mode 有权

    公开(公告)号：US11243897B2

    公开(公告)日：2022-02-08

    申请号：US16862916

    申请日：2020-04-30

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Abhijit Abhyankar ,  Suresh Rajan

    IPC: G06F13/16 ,  G06F11/20 ,  G06F13/00 ,  G06F13/42

    Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

    High performance, high capacity memory modules and systems
    57.
    发明授权
    High performance, high capacity memory modules and systems 有权

    公开(公告)号：US10678459B2

    公开(公告)日：2020-06-09

    申请号：US15745396

    申请日：2016-07-14

    Applicant: Rambus Inc.

    Inventor： Suresh Rajan ,  Abhijit M. Abhyankar ,  Ravindranath Kollipara ,  David A. Secker

    IPC: G06F3/06 ,  G06F13/16

    Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

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