PROTOCOLS FOR HIGH PERFORMANCE COMPUTING VISUALIZATION, COMPUTATIONAL STEERING AND FORWARD PROGRESS
    51.
    发明申请
    PROTOCOLS FOR HIGH PERFORMANCE COMPUTING VISUALIZATION, COMPUTATIONAL STEERING AND FORWARD PROGRESS 失效
    高性能计算可视化,计算转向和前进进程的协议

    公开(公告)号:US20100262882A1

    公开(公告)日:2010-10-14

    申请号:US12422422

    申请日:2009-04-13

    IPC分类号: H04L1/08 G06F11/14

    摘要: Methods, systems and computer program product for reducing latency and increasing throughput of data transmissions along a switch network path. Exemplary embodiments include a method in a network accelerator device having a memory buffer, a method including identifying a data transmission, copying data packets from the data transmission into the memory buffer, and in response to at least one of a missing data packet and a corrupt data packet identified during the data transmission, sending a copied data packet corresponding to the at least one of the missing data packet and the corrupt data packet.

    摘要翻译: 方法,系统和计算机程序产品,用于减少交换机网络路径上的数据传输的延迟和增加吞吐量。 示例性实施例包括具有存储器缓冲器的网络加速器装置中的方法,包括识别数据传输的方法,将数据分组从数据传输复制到存储器缓冲器中,以及响应于丢失数据分组和损坏中的至少一个 在数据传输期间识别的数据分组,发送对应于丢失数据分组和损坏数据分组中的至少一个的复制数据分组。

    TARGET COMPUTER PROCESSOR UNIT (CPU) DETERMINATION DURING CACHE INJECTION USING INPUT/OUTPUT (I/O) HUB/CHIPSET RESOURCES
    53.
    发明申请
    TARGET COMPUTER PROCESSOR UNIT (CPU) DETERMINATION DURING CACHE INJECTION USING INPUT/OUTPUT (I/O) HUB/CHIPSET RESOURCES 失效
    目标计算机处理器单元(CPU)使用输入/输出(I / O)HUB / CHIPSET资源进行高速缓存注入期间的确定

    公开(公告)号:US20090157979A1

    公开(公告)日:2009-06-18

    申请号:US11958435

    申请日:2007-12-18

    IPC分类号: G06F12/08

    CPC分类号: G06F12/0897 G06F12/0831

    摘要: A method, system, and computer program product for target computer processor unit (CPU) determination during cache injection using I/O hub/chipset resources are provided. The method includes creating a cache injection indirection table on the input/output (I/O) hub or chipset. The cache injection indirection table includes fields for address or address range, CPU identifier, and cache type. In response to receiving an input/output (I/O) transaction, the hub/chipset reads the address in an address field of the I/O transaction, looks up the address in the cache injection indirection table, and injects the address and data of the I/O transaction to a target cache associated with a CPU as identified in the CPU identifier field when, in response to the look up, the address is present in the address field of the cache injection indirection table.

    摘要翻译: 提供了使用I / O集线器/芯片组资源的高速缓存注入期间的目标计算机处理器单元(CPU)确定的方法,系统和计算机程序产品。 该方法包括在输入/输出(I / O)集线器或芯片组上创建高速缓存注入间接表。 高速缓存注入间接表包括用于地址或地址范围,CPU标识符和缓存类型的字段。 响应于接收到输入/输出(I / O)事务,集线器/芯片组读取I / O事务的地址字段中的地址,查找缓存注入间接表中的地址,并注入地址和数据 的I / O事务发送到与CPU标识符字段中所标识的CPU相关联的目标缓存器,当响应于查找时,地址存在于高速缓存注入间接表的地址字段中。

    CACHE INJECTION USING SPECULATION
    54.
    发明申请
    CACHE INJECTION USING SPECULATION 有权
    使用规范进行缓存注入

    公开(公告)号:US20090157966A1

    公开(公告)日:2009-06-18

    申请号:US11958440

    申请日:2007-12-18

    IPC分类号: G06F12/08

    摘要: A method, system, and computer program product for cache injection using speculation are provided. The method includes creating a cache line indirection table at an input/output (I/O) hub, which includes fields and entries for addresses, processor ID, and cache type and includes cache level line limit fields. The method also includes setting cache line limits to the CLL fields and receiving a stream of contiguous addresses at the table. For each address in the stream, the method includes: looking up the address in the table; if the address is present in the table, inject the cache line corresponding to the address in the processor complex; if the address is not present in the table, search limit values from the lowest level cache to the highest level cache; and inject addresses not present in the table to the cache hierarchy of the processor last injected from the contiguous address stream.

    摘要翻译: 提供了一种使用推测进行缓存注入的方法,系统和计算机程序产品。 该方法包括在输入/输出(I / O)集线器处创建高速缓存行间接表,其包括用于地址,处理器ID和高速缓存类型的字段和条目,并且包括高速缓存级别线限制字段。 该方法还包括为CLL字段设置高速缓存行限制并在表中接收连续地址流。 对于流中的每个地址,该方法包括:查找表中的地址; 如果地址存在于表中,则将与地址对应的缓存线注入处理器复合体; 如果表中不存在地址,则从最低级缓存搜索极限值到最高级缓存; 并将表中不存在的地址注入到从连续地址流最后注入的处理器的高速缓存层级。

    Reservation system for an ethernet network
    56.
    发明授权
    Reservation system for an ethernet network 有权
    以太网网络预留系统

    公开(公告)号:US09094345B2

    公开(公告)日:2015-07-28

    申请号:US13362749

    申请日:2012-01-31

    IPC分类号: H04L12/911 H04L12/927

    摘要: An improved computer system may include a server carrying a computer processor in a Fiber Channel over Convergence Enhanced Ethernet (FCoCEE) network. The system may also include a reservation system in communication with the server that utilizes enhanced transmission selection (ETS) to reserve bandwidth for a priority group by scheduling bandwidth for the priority group based upon a projected workload.

    摘要翻译: 改进的计算机系统可以包括承载光纤通道在融合增强以太网(FCoCEE)网络上的计算机处理器的服务器。 该系统还可以包括与服务器通信的预留系统,其利用增强的传输选择(ETS)来基于预计的工作负载调度优先级组的带宽来为优先级组预留带宽。

    System to improve an ethernet network
    57.
    发明授权
    System to improve an ethernet network 有权
    系统改进以太网网络

    公开(公告)号:US09007904B2

    公开(公告)日:2015-04-14

    申请号:US13299336

    申请日:2011-11-17

    摘要: A system to improve a Fiber Channel over Convergence Enhanced Ethernet (FCoCEE) network may include a sender in an FCoCEE network in which data packets having different data link layer structures are transmitted by the sender on a single data link. The system may also include a receiver to receive the data packets at the data link layer and to transmit an ACK and/or NAK in response to a sequence number in the data packets. The system may further include a replay buffer to retransmit the data packets where the replay buffer is sized by the length of the data link, data rate of the data link, the ACK and/or NAK processing time at either the sender and/or the receiver, and/or a threshold time for transmission and/or reception of the data packets.

    摘要翻译: 改进光纤通道收敛增强型以太网(FCoCEE)网络的系统可能包括FCoCEE网络中的发送方,其中具有不同数据链路层结构的数据分组由发送方在单个数据链路上传输。 系统还可以包括接收器,用于在数据链路层接收数据分组,并响应于数据分组中的序列号来发送ACK和/或NAK。 该系统可以进一步包括一个重放缓冲器,用于重传数据分组,其中重播缓冲器的大小取决于数据链路的长度,数据链路的数据速率,ACK和/或NAK处理时间在发送方和/或 接收器和/或用于传输和/或接收数据分组的阈值时间。

    Redundant power supply configuration for a data center
    58.
    发明授权
    Redundant power supply configuration for a data center 失效
    数据中心的冗余电源配置

    公开(公告)号:US08671287B2

    公开(公告)日:2014-03-11

    申请号:US12821226

    申请日:2010-06-23

    IPC分类号: G06F1/00

    摘要: A redundant power supply configuration for a data center is provided. A method includes receiving instructions to operate power supplies at a high current mode. An individual current for each of the power supplies is calculated to total a high current at the high current mode. The power supplies are operated at the high current mode to provide the high current at the high current mode. In response to operation at the high current mode being complete, the power supplies are operated at a normal mode to provide a normal current at the normal current mode.

    摘要翻译: 提供了数据中心的冗余电源配置。 一种方法包括接收以高电流模式操作电源的指令。 计算每个电源的单独电流,以在高电流模式下总计高电流。 电源以高电流模式工作,以提供高电流模式下的高电流。 响应于高电流模式下的操作完成,电源在正常模式下操作以在正常电流模式下提供正常电流。

    Managing accelerators of a computing environment
    60.
    发明授权
    Managing accelerators of a computing environment 有权
    管理计算环境的加速器

    公开(公告)号:US08423799B2

    公开(公告)日:2013-04-16

    申请号:US12627050

    申请日:2009-11-30

    摘要: Accelerators of a computing environment are managed in order to optimize energy consumption of the accelerators. To facilitate the management, virtual queues are assigned to the accelerators, and a management technique is used to enqueue specific tasks on the queues for execution by the corresponding accelerators. The management technique considers various factors in determining which tasks to be placed on which virtual queues in order to manage energy consumption of the accelerators.

    摘要翻译: 管理计算环境的加速器以便优化加速器的能量消耗。 为了便于管理,将虚拟队列分配给加速器,并且使用管理技术来排队队列中的特定任务以由相应的加速器执行。 管理技术考虑了决定哪些任务放置在哪些虚拟队列上以管理加速器的能量消耗的各种因素。