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159 条记录 (耗时 0.038 秒)

    Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistors
    51.
    发明授权
    Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistors 失效
    在紧密间隔的晶体管的接触电平中的介电材料的图案化期间减小与形貌相关的不规则性的技术

    公开(公告)号：US08338314B2

    公开(公告)日：2012-12-25

    申请号：US12372006

    申请日：2009-02-17

    申请人： Ralf Richter ,  Heike Salz ,  Robert Seidel

    发明人： Ralf Richter ,  Heike Salz ,  Robert Seidel

    IPC分类号： H01L21/31

    CPC分类号： H01L21/02107 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/51 ,  H01L29/7843 ,  H01L29/7848 ,  Y02P80/30

    摘要： In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond.

    摘要翻译： 在双重应力衬垫方法中，可以通过适当地设计用于基本上完全去除蚀刻停止材料的蚀刻顺序来增强第一应力诱导层的图案化之后的表面状态，所述蚀刻顺序可用于图案化第二应力 - 诱导介电材料，而在其它情况下，可以在第一应力诱导电介质材料的图案化之后选择性地形成蚀刻停止材料。 因此，双重应力衬垫方法可以有效地应用于45nm技术及其以外的半导体器件。

    Using high-k dielectrics as highly selective etch stop materials in semiconductor devices
    53.
    发明授权
    Using high-k dielectrics as highly selective etch stop materials in semiconductor devices 有权
    使用高k电介质作为半导体器件中的高选择性蚀刻停止材料

    公开(公告)号：US08198166B2

    公开(公告)日：2012-06-12

    申请号：US12844135

    申请日：2010-07-27

    申请人： Thorsten Kammler ,  Ralf Richter ,  Markus Lenski ,  Gunter Grasshoff

    发明人： Thorsten Kammler ,  Ralf Richter ,  Markus Lenski ,  Gunter Grasshoff

    IPC分类号： H01L21/00

    CPC分类号： H01L29/4983 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843

    摘要： A spacer structure in sophisticated semiconductor devices is formed on the basis of a high-k dielectric material, which provides superior etch resistivity compared to conventionally used silicon dioxide liners. Consequently, a reduced thickness of the etch stop material may nevertheless provide superior etch resistivity, thereby reducing negative effects, such as dopant loss in the drain and source extension regions, creating a pronounced surface topography and the like, as are typically associated with conventional spacer material systems.

    摘要翻译： 在高k电介质材料的基础上形成复杂半导体器件中的间隔结构，其与传统使用的二氧化硅衬垫相比提供了优异的蚀刻电阻率。 因此，蚀刻停止材料的厚度减小可以提供优异的蚀刻电阻率，从而减少负面影响，例如漏极和源极延伸区域中的掺杂剂损失，产生显着的表面形貌等，如通常与常规间隔物相关联 材料系统

    USING HIGH-K DIELECTRICS AS HIGHLY SELECTIVE ETCH STOP MATERIALS IN SEMICONDUCTOR DEVICES
    58.
    发明申请
    USING HIGH-K DIELECTRICS AS HIGHLY SELECTIVE ETCH STOP MATERIALS IN SEMICONDUCTOR DEVICES 有权
    使用高K电介质作为半导体器件中的高选择性止蚀材料

    公开(公告)号：US20110024805A1

    公开(公告)日：2011-02-03

    申请号：US12844135

    申请日：2010-07-27

    申请人： Thorsten Kammler ,  Ralf Richter ,  Markus Lenski ,  Gunter Grasshoff

    发明人： Thorsten Kammler ,  Ralf Richter ,  Markus Lenski ,  Gunter Grasshoff

    IPC分类号： H01L29/40 ,  H01L21/3065 ,  H01L21/266

    CPC分类号： H01L29/4983 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843

    摘要： A spacer structure in sophisticated semiconductor devices is formed on the basis of a high-k dielectric material, which provides superior etch resistivity compared to conventionally used silicon dioxide liners. Consequently, a reduced thickness of the etch stop material may nevertheless provide superior etch resistivity, thereby reducing negative effects, such as dopant loss in the drain and source extension regions, creating a pronounced surface topography and the like, as are typically associated with conventional spacer material systems.

    摘要翻译： 在高k电介质材料的基础上形成复杂半导体器件中的间隔结构，其与传统使用的二氧化硅衬垫相比提供了优异的蚀刻电阻率。 因此，蚀刻停止材料的厚度减小可以提供优异的蚀刻电阻率，从而减少负面影响，例如漏极和源极延伸区域中的掺杂剂损失，产生显着的表面形貌等，如通常与常规间隔物相关联 材料系统

    Technique for compensating for a difference in deposition behavior in an interlayer dielectric material
    60.
    发明授权
    Technique for compensating for a difference in deposition behavior in an interlayer dielectric material 有权
    补偿层间电介质材料沉积行为差异的技术

    公开(公告)号：US07785956B2

    公开(公告)日：2010-08-31

    申请号：US12168443

    申请日：2008-07-07

    申请人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    发明人： Ralf Richter ,  Robert Seidel ,  Carsten Peters

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/7843

    摘要： By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.

    摘要翻译： 通过选择性地提供具有适当厚度的缓冲层，在形成先进的半导体器件的层间电介质叠层的过程中，可以减少沉积SACVD二氧化硅期间出现的高度差异。 可以在沉积两种类型的内部应力的接触蚀刻停止层之后选择性地提供缓冲材料，或者可以在沉积一种类型的电介质材料之后提供缓冲材料，并且可以在随后的其它类型的电介质停止材料的图案化期间使用缓冲材料 作为有效的蚀刻停止层。