公开(公告)号：US06727839B2

公开(公告)日：2004-04-27

申请号：US10226165

申请日：2002-08-23

Applicant: Jan Mulder ,  Franciscus M. L. van der Goes

Inventor： Jan Mulder ,  Franciscus M. L. van der Goes

IPC: H03M134

CPC classification number: H03M1/0863 ,  H03M1/36

Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.

Abstract translation: 一种用于减少具有比较器阵列的模数转换器中的位错误的方法。 第一和第二比较器的输出在异或门的输入中被接收。 第一和第二比较器由阵列中的第三比较器分开。 异或门的输出用于确定第三比较器是否处于亚稳态。 如果第三比较器处于亚稳态，则第三比较器的锁存电路的偏置电流增加，以增加第三比较器转变到稳定状态的速率。

公开(公告)号：US06720798B2

公开(公告)日：2004-04-13

申请号：US10158193

申请日：2002-05-31

Applicant: Jan Mulder ,  Yee Ling Cheung

Inventor： Jan Mulder ,  Yee Ling Cheung

IPC: H03K522

CPC classification number: H03K17/04106 ,  H03M1/146 ,  H03M1/204 ,  H03M1/365 ,  H03M1/742 ,  H04L25/026 ,  H04L25/0276

Abstract: A differential line driver includes first, second, third and fourth cascode transistors connected in parallel, wherein drains of the first and third transistors are connected to a negative output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a positive output of the differential line driver. First, second, third and fourth switching transistors are connected in series with corresponding first, second, third and fourth cascode transistors and driven by a data signal. First and second compound transistors inputting a class AB operation signal at their gates, wherein the first compound transistor is connected to sources of the first and second switching transistors, and wherein the second compound transistor is connected to sources of the third and fourth switching transistors.

公开(公告)号：US06674388B2

公开(公告)日：2004-01-06

申请号：US10349073

申请日：2003-01-23

Applicant: Jan Mulder

Inventor： Jan Mulder

IPC: H03M114

CPC classification number: H03M1/0863 ,  H03K17/04106 ,  H03M1/146 ,  H03M1/204 ,  H03M1/36 ,  H03M1/365

Abstract: An analog to digital converter includes a reference ladder, a track-and-hold amplifier tracking an input signal with its output signal during the phase &phgr;1 and holding a sampled value during, a coarse analog to digital converter having a plurality of coarse amplifiers each inputting a corresponding tap from the reference ladder and the output signal, a fine analog-to-digital converter having a plurality of fine amplifiers inputting corresponding taps from the reference ladder and the output signal, the taps selected based on outputs of the coarse amplifiers, a clock having phases &phgr;1 and &phgr;2, a circuit responsive to the clock that receives the output signal, the circuit substantially passing the output signal and the corresponding taps to the fine amplifiers during the phase &phgr;2 and substantially rejecting the output signal and the corresponding taps during the phase &phgr;1, and an encoder converting outputs of the coarse and fine amplifiers to an N-bit digital signal representing the input signal.

Abstract translation: 模数转换器包括参考梯形图，跟踪和保持放大器，在相位phi1期间跟踪具有其输出信号的输入信号并保持采样值，粗略模数转换器具有多个粗放大器，每个粗放大器输入 来自参考梯形图和输出信号的对应抽头，具有多个精细放大器的精细模数转换器，该精细放大器从参考梯形图输入相应的抽头和输出信号，基于粗放大器的输出选择的抽头， 具有相位phi1和phi2的时钟，响应于接收输出信号的时钟的电路，电路在相位phi2期间基本上将输出信号和相应的抽头传递到精细放大器，并在该期间基本上拒绝输出信号和对应的抽头 相位phi1和将粗略和精细放大器的输出转换成表示th的N位数字信号的编码器 e输入信号。

公开(公告)号：US06664910B1

公开(公告)日：2003-12-16

申请号：US10460622

申请日：2003-06-13

Applicant: Jan Mulder ,  Christopher Michael Ward

Inventor： Jan Mulder ,  Christopher Michael Ward

IPC: H03M112

CPC classification number: H03K17/04106 ,  H03M1/0646 ,  H03M1/146 ,  H03M1/204 ,  H03M1/206 ,  H03M1/361 ,  H03M1/365

Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

公开(公告)号：US06653966B1

公开(公告)日：2003-11-25

申请号：US10359201

申请日：2003-02-06

Applicant: Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Rudy van de Plassche ,  Marcel Lugthart

Inventor： Franciscus Maria Leonardus van der Goes ,  Jan Mulder ,  Christopher Michael Ward ,  Jan Roelof Westra ,  Rudy van de Plassche ,  Marcel Lugthart

IPC: H03M100

CPC classification number: H03M1/146 ,  H03K17/04106 ,  H03M1/204 ,  H03M1/365

Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

Abstract translation: N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关 两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围 参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出 其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

公开(公告)号：US06642794B2

公开(公告)日：2003-11-04

申请号：US09920117

申请日：2001-08-01

Applicant: Jan Mulder ,  Dominicus Martinus Wilhelmus Leenaerts ,  Edwin Van Der Heijden

Inventor： Jan Mulder ,  Dominicus Martinus Wilhelmus Leenaerts ,  Edwin Van Der Heijden

IPC: H03F368

CPC classification number: H03F3/343 ,  H03F1/22 ,  H03F2200/372

Abstract: An amplifier, in particular an RF amplifier is described having an amplifier input, the amplifier comprises: a first controllable semiconductor having a first controllable mainstream path coupled to first source means for controlling the first mainstream path, and having a first biased control input; and a second controllable semiconductor having a second controllable mainstream path coupled to second source means for controlling the second mainstream path, and having a second control input coupled to the first main stream path and to the amplifier input. Both the first and second mainstream paths are coupled to a common load, and the first and second source means are arranged for controlling input impedance and noise impedance respectively of the amplifier input. This amplifier arrangement allows independent control and optimisation of both the amplifier input impedance and the noise impedance.

公开(公告)号：US06392478B1

公开(公告)日：2002-05-21

申请号：US09713864

申请日：2000-11-16

Applicant: Jan Mulder ,  Marcel Louis Lugthart

Inventor： Jan Mulder ,  Marcel Louis Lugthart

IPC: H03F136

CPC classification number: H03G1/0088 ,  G11B5/00 ,  G11B20/10009 ,  G11B2005/0016 ,  G11B2005/0018

Abstract: The invention relates to a device for amplifying electronic signals, including: an amplifier PRA, and a plurality of feedback loops G1, G2 placed between the output and the input of the amplifier, which feedback loops are arranged so that each feedback loop has an adjustable gain and all the feedback loops jointly form an assembly having an equivalent impedance which is substantially independent of the gain settings selected. Thanks to the invention, the amplification bandwidth can be easily adjusted without adversely affecting the performance of the device in terms of noise and high cut-off frequency.

Abstract translation: 本发明涉及一种用于放大电子信号的装置，包括：放大器PRA和放置在放大器的输出端和输入端之间的多个反馈回路G1，G2，该反馈回路被布置成使得每个反馈回路具有可调增益 并且所有的反馈回路共同形成具有基本上与选择的增益设置无关的等效阻抗的组件。由于本发明，可以容易地调整放大带宽，而不会对器件在噪声和高切割方面的性能产生不利影响 关闭频率

公开(公告)号：US08986453B2

公开(公告)日：2015-03-24

申请号：US12664648

申请日：2008-06-13

Applicant: Johannes Käppeler ,  Adam Boyd ,  Victor Saywell ,  Jan Mulder ,  Olivier Feron

Inventor： Johannes Käppeler ,  Adam Boyd ,  Victor Saywell ,  Jan Mulder ,  Olivier Feron

IPC: B05C11/00 ,  C23C16/458 ,  C23C16/46 ,  C30B25/12 ,  H01L21/687

CPC classification number: C23C16/4586 ,  C23C16/4583 ,  C23C16/46 ,  C30B25/12 ,  H01L21/68735

Abstract: The invention relates to a device for coating substrates having a process chamber (1) disposed in a reactor housing and a two-part, substantially cup-shaped susceptor (2, 3) disposed therein, forming an upper susceptor part (2) with the cup floor thereof having a flat plate (2′) and a lower susceptor part (3) with the cup side walls thereof, the outer side (4) of the plate (2′) of the upper susceptor part (2) facing upwards toward the process chamber (1) and forming a contact surface for at least one substrate, the upper susceptor part (2) contacting a front edge (3″) of the lower susceptor part (3) at the edge of said upper susceptor part (2), the lower susceptor part (3) being supported by a susceptor carrier (6), and heating zones (A, B, C) for heating the upper susceptor part (2) being disposed below the plate (2′). An advantageous refinement of the invention proposes that the upper susceptor part (2) be removable from the process chamber (1) separately from the lower susceptor part (3), and the joint (30) between the edge of the upper susceptor part (2) and the front edge (3″) of the lower susceptor part (3) be formed as a heat conduction barrier.

Abstract translation: 本发明涉及一种用于涂覆基材的装置，其具有设置在反应器壳体中的处理室（1）和设置在反应器壳体中的两部分基本杯形基座（2,3），形成上基座部分（2），其中 其底板具有平板（2'）和具有杯侧壁的下基座部分（3），上托架部分（2）的板（2'）的外侧（4）朝向 所述处理室（1）并且形成用于至少一个基板的接触表面，所述上基座部分（2）在所述上基座部分（2）的边缘处接触所述下基座部分（3）的前边缘（3“）， ），下感受器部分（3）由基座托架（6）支撑，加热区（A，B，C）用于加热设置在板（2'）下方的上基座部分（2）。 本发明的有益改进提出，上基座部分（2）可以与下基座部分（3）分离地从处理室（1）移除，并且上基座部分（2）的边缘之间的接头（30） ）和下基座部（3）的前缘（3“）形成为导热屏障。

公开(公告)号：US07616144B2

公开(公告)日：2009-11-10

申请号：US11857417

申请日：2007-09-18

Applicant: Jan Mulder ,  Franciscus Maria Leonardus van der Goes ,  Jan Westra ,  Rudy van der Plassche

Inventor： Jan Mulder ,  Franciscus Maria Leonardus van der Goes ,  Jan Westra ,  Rudy van der Plassche

IPC: H03M1/78

CPC classification number: H03K17/04106 ,  H03M1/204 ,  H03M1/365

Abstract: A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.

Abstract translation: 电压内插电路包括连接在地和电压输入端之间的电阻梯形电阻，并具有多个电阻器，电阻器之间具有电压抽头。 放大器（可选地）具有在其相应的第一端子和放大器的输入端连接在一起的第一和第二电容器。 第一多个开关将各个抽头连接到第一电容器的第二端子。 第二多个开关将各个抽头连接到第二电容器的第二端子。 通过控制第一和第二多个开关来内插输出电压。

公开(公告)号：US07587181B2

公开(公告)日：2009-09-08

申请号：US10986020

申请日：2004-11-12

Applicant: Yee Ling Cheung ,  Kevin T. Chan ,  Jan Mulder

Inventor： Yee Ling Cheung ,  Kevin T. Chan ,  Jan Mulder

IPC: H04B1/04

CPC classification number: H04B1/581

Abstract: Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The transmitter includes a plurality of current cells. Each cell is configurable for operating in different modes. The method includes determining a first probability associated with transmitting data at a particular symbolic level and determining a second probability associated with each cell being used during a transmission at the particular symbolic level. Next, one of the modes for each cell is selected in accordance with anticipated performance requirements. An average current of the transmitter is then calculated based upon the determined first and second probabilities and the selected modes.

Abstract translation: 提供了一种用于控制具有发射机的收发机中的电流特性的方法和系统。 发射机包括多个当前小区。 每个单元都可配置为以不同的模式运行。 该方法包括确定与在特定符号级别发送数据相关联的第一概率，并且确定与在特定符号级别的传输期间正在使用的每个小区相关联的第二概率。 接下来，根据预期的性能要求选择每个单元的模式之一。 然后基于所确定的第一和第二概率和所选择的模式来计算发射机的平均电流。