公开(公告)号：US08779360B2

公开(公告)日：2014-07-15

申请号：US13809923

申请日：2011-06-22

申请人： Kozo Miyake ,  Junko Konishi ,  Takehiro Hirai ,  Kenji Obara

发明人： Kozo Miyake ,  Junko Konishi ,  Takehiro Hirai ,  Kenji Obara

IPC分类号： H01J37/153

CPC分类号： H01J37/153 ,  G01N23/00 ,  H01J37/28 ,  H01J2237/24592 ,  H01J2237/2817

摘要： Provided is a charged particle beam device that prevents the increase in processing trouble caused by deterioration in the reviewing performance (e.g., overlooking of defects) by detecting an operation abnormality affecting the performance of the device or a possibility of such an abnormality in the middle of a processing sequence of a sample and giving a feedback in real time. In each processing step of the charged particle beam device, monitoring items representing the operating status of the device (control status of the electron beam, an offset amount at the time of wafer positioning, a defect coordinate error offset amount, etc.) are monitored during the processing sequence of a sample and stored as history information. In the middle of the processing sequence, a comparative judgment between the value of each monitoring item and the past history information corresponding to the monitoring item is made according to preset judgment criteria. When the width of fluctuation from the past history information deviates from a reference range, an alert is issued.

摘要翻译： 提供了一种带电粒子束装置，其通过检测影响装置的性能的操作异常或在中间的这种异常的可能性来防止由于检查性能的劣化（例如，忽视缺陷）引起的加工故障的增加 样品的处理顺序并实时提供反馈。 在带电粒子束装置的每个处理步骤中，监视表示装置的运行状态（电子束的控制状态，晶片定位时的偏移量，缺陷坐标误差偏移量等）的监视项目 在样品的处理顺序期间并存储为历史信息。 在处理顺序的中间，根据预先设定的判断基准，进行各监视项目的值与对应于监视项目的过去历史信息的比较判断。 当过去历史信息的波动宽度偏离参考范围时，发出警报。

公开(公告)号：US20130112893A1

公开(公告)日：2013-05-09

申请号：US13809923

申请日：2011-06-22

申请人： Kozo Miyake ,  Junko Konishi ,  Takehiro Hirai ,  Kenji Obara

发明人： Kozo Miyake ,  Junko Konishi ,  Takehiro Hirai ,  Kenji Obara

IPC分类号： G01N23/00

CPC分类号： H01J37/153 ,  G01N23/00 ,  H01J37/28 ,  H01J2237/24592 ,  H01J2237/2817

摘要： Provided is a charged particle beam device that prevents the increase in processing trouble caused by deterioration in the reviewing performance (e.g., overlooking of defects) by detecting an operation abnormality affecting the performance of the device or a possibility of such an abnormality in the middle of a processing sequence of a sample and giving a feedback in real time. In each processing step of the charged particle beam device, monitoring items representing the operating status of the device (control status of the electron beam, an offset amount at the time of wafer positioning, a defect coordinate error offset amount, etc.) are monitored during the processing sequence of a sample and stored as history information. In the middle of the processing sequence, a comparative judgment between the value of each monitoring item and the past history information corresponding to the monitoring item is made according to preset judgment criteria. When the width of fluctuation from the past history information deviates from a reference range, an alert is issued.

摘要翻译： 提供了一种带电粒子束装置，其通过检测影响装置的性能的操作异常或在中间的这种异常的可能性来防止由于检查性能的劣化（例如，忽视缺陷）引起的加工故障的增加 样品的处理顺序并实时提供反馈。 在带电粒子束装置的每个处理步骤中，监视表示装置的运行状态（电子束的控制状态，晶片定位时的偏移量，缺陷坐标误差偏移量等）的监视项目 在样品的处理顺序期间并存储为历史信息。 在处理顺序的中间，根据预先设定的判断基准，进行各监视项目的值与对应于监视项目的过去历史信息的比较判断。 当过去历史信息的波动宽度偏离参考范围时，发出警报。

公开(公告)号：US07752001B2

公开(公告)日：2010-07-06

申请号：US11753966

申请日：2007-05-25

申请人： Takehiro Hirai ,  Kazuo Aoki ,  Kumi Kaneko

发明人： Takehiro Hirai ,  Kazuo Aoki ,  Kumi Kaneko

IPC分类号： G01C17/38 ,  G21C17/00

CPC分类号： G01R31/2884

摘要： The present invention provides a method of correcting coordinates so as to quickly and properly arrange a sample in a field of view in a review apparatus for moving a sample stage onto the specified coordinates to review the sample. A review apparatus according to the present invention, which is a review apparatus for moving a sample stage onto coordinates previously calculated by a checking apparatus to review the sample, has a function of retaining a plurality of coordinate correction tables to correct a deviation between a coordinate value previously calculated by a checking apparatus and an actual sample position detected by the review apparatus. The review apparatus evaluates correction accuracy of the plurality of coordinate correction tables and applies one of the coordinate correction tables with the maximum evaluation value.

摘要翻译： 本发明提供了一种校正坐标的方法，以便在用于将样品台移动到特定坐标上以检查样品的检查装置中的视场中快速且适当地布置样品。 根据本发明的检查装置，其是用于将样本台移动到由检查装置预先计算的坐标以检查样本的检查装置，具有保留多个坐标校正表以校正坐标的偏差的功能 先前由检查装置计算的值和由检查装置检测到的实际样品位置。 评估装置评估多个坐标校正表的校正精度，并且应用具有最大评估值的坐标校正表中的一个。

公开(公告)号：US20080270044A1

公开(公告)日：2008-10-30

申请号：US12108068

申请日：2008-04-23

申请人： Takehiro Hirai ,  Kenji Obara ,  Kohei Yamaguchi

发明人： Takehiro Hirai ,  Kenji Obara ,  Kohei Yamaguchi

IPC分类号： G01B11/03 ,  G06F19/00

CPC分类号： H01J37/265 ,  H01J37/28 ,  H01J2237/221 ,  H01J2237/2817 ,  H01J2237/2826

摘要： The present invention aims to provide a defect review apparatus capable of suppressing a reduction in throughput with a minimized deviation-amount measurement, and capable of optimizing an FOV of a monitoring image. To this end, the review apparatus for reviewing a specimen by moving the specimen to pre-calculated coordinate includes: a function to measure a deviation amount between the pre-calculated coordinates and coordinates of an actual position of the specimen; a function to optimize a coordinate correcting expression to minimize the measured deviation amount; and a function to determine that the deviation amounts have converged. When the deviation amounts have converged, the measurement for the coordinate-correcting-expression optimization is terminated. Thereby, the reduction in throughput is suppressed to the minimum level, and furthermore a FOV necessary for the specimen to be within the field of view is set according to a convergence value of the calculated deviation amount.

摘要翻译： 本发明的目的在于提供一种缺陷检查装置，其能够以最小化的偏差量测量来抑制吞吐量的降低，并能够优化监视图像的FOV。 为此，用于通过将样本移动到预先计算的坐标来检查样本的检查装置包括：测量预先计算的坐标与样本的实际位置的坐标之间的偏差量的函数; 优化坐标校正表达式以最小化所测量的偏差量的函数; 以及确定偏差量已经收敛的函数。 当偏差量收敛时，终止坐标校正表达式优化的测量。 由此，将吞吐量的降低抑制到最小水平，并且根据计算出的偏差量的收敛值来设定样本在视野范围内所需的FOV。

公开(公告)号：US6140687A

公开(公告)日：2000-10-31

申请号：US979559

申请日：1997-11-26

申请人： Hiroshi Shimomura ,  Takehiro Hirai ,  Joji Hayashi ,  Takashi Nakamura

发明人： Hiroshi Shimomura ,  Takehiro Hirai ,  Joji Hayashi ,  Takashi Nakamura

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/94

CPC分类号： H01L27/0207 ,  H01L23/4824 ,  H01L29/0692 ,  H01L29/1087 ,  H01L29/41758 ,  H01L29/4238 ,  H01L2924/0002

摘要： In an active area surrounded with an isolation formed on a silicon substrate, a large number of unit cells are disposed in a matrix, and the unit cell together form one MOSFET. Each of the unit includes a ring gate electrode in the shape of a regular octagon, a drain region and a source region formed at the inside and outside of the gate electrode, respectively, two gate withdrawn wires extending from the gate electrode to area above the isolation, a substrate contact portion in which the surface of the substrate is exposed, and contacts for electrically connecting these elements with wires. These elements such as the ring gate electrode and the gate withdrawn wires are formed so as to attain a high frequency characteristic as good as possible. Thus a MOSFET for use in a high frequency signal device, the high frequency characteristic such as the minimum noise figure and the maximum oscillation frequency in particular can be totally improved.

摘要翻译： 在由硅衬底上形成的隔离物包围的有源区域中，大量的单元电池被设置在矩阵中，并且单位电池一起形成一个MOSFET。 每个单元包括分别形成在栅电极的内部和外部的规则八边形，漏极区域和源极区域形状的环形栅极电极，从栅极电极延伸到区域上方的两个栅极引出线 隔离，其中基板的表面露出的基板接触部分和用于将这些元件与电线电连接的触点。 这些元件如环形栅电极和栅极引出线形成为尽可能地获得高频特性。 因此，用于高频信号装置的MOSFET可以完全改善诸如最小噪声系数和最大振荡频率的高频特性。

公开(公告)号：US5838048A

公开(公告)日：1998-11-17

申请号：US915327

申请日：1997-08-20

申请人： Takehiro Hirai ,  Masahiro Nakatani ,  Mitsuo Tanaka ,  Akihiro Kanda

发明人： Takehiro Hirai ,  Masahiro Nakatani ,  Mitsuo Tanaka ,  Akihiro Kanda

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L29/51 ,  H01L27/02 ,  H01L29/68

CPC分类号： H01L29/513 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/518 ,  Y10S148/009

摘要： A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are patterned to form an emitter electrode and a gate electrode made of the two polysilicon films which are doped with arsenic. The arsenic is diffused from the polysilicon films of the emitter electrode into the silicon substrate to form an N.sup.+ emitter layer which has a high concentration and is shallow. Consequently, the contamination of a gate insulator film can be prevented from occurring and a bipolar transistor having high performance, for example, a high current amplification factor or the like can be formed.

摘要翻译： 在硅衬底上形成氧化硅膜和多晶硅膜，并且被选择性地蚀刻以在要形成发射极的区域中形成接触孔。 将多晶硅膜放置在衬底上，并且将两个多晶硅膜图案化以形成由掺杂有砷的两个多晶硅膜制成的发射极电极和栅极电极。 砷从发射电极的多晶硅膜扩散到硅衬底中以形成具有高浓度且浅的N +发射极层。 因此，可以防止栅极绝缘膜的污染，并且可以形成具有高性能的双极晶体管，例如高电流放大因子等。

公开(公告)号：US5817551A

公开(公告)日：1998-10-06

申请号：US701913

申请日：1996-08-23

申请人： Taizo Fujii ,  Takehiro Hirai ,  Sugao Fujinaga

发明人： Taizo Fujii ,  Takehiro Hirai ,  Sugao Fujinaga

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L21/26586 ,  H01L21/823412 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/66674 ,  H01L29/7801 ,  H01L29/1095

摘要： In forming a P.sup.- body diffused layer in a portion on the source side of an N.sup.- drain diffused layer of a DMOSFET, P-type impurity ions are implanted at a large tilt angle to reach a part of a region underlying an N.sup.+ gate electrode by using, as a mask, a resist film having an opening corresponding to a region in which the body diffused layer of the DMOSFET is to be formed and the N.sup.+ gate electrode so as to be activated. Thereafter, an N.sup.+ source diffused layer and an N.sup.+ drain diffused layer are formed in the P.sup.- body diffused layer and in the N.sup.- drain diffused layer, respectively. Since a high-temperature drive-in process need not be performed to introduce the P-type impurity ions into the region underlying the N.sup.+ gate electrode, a reduction or variations in threshold voltage and the degradation of a gate oxide film each caused by the impurity diffused from the N.sup.+ gate electrode can be prevented. Consequently, there is provided a semiconductor device having a DMOSFET mounted thereon which has a reduced on-resistance and suppresses the activation of a parasitic bipolar transistor due to reduced variations in threshold voltage and a high-quality gate oxide film.

摘要翻译： 在DMOSFET的N-漏极扩散层的源极侧的部分中形成P-体扩散层时，以大的倾斜角注入P型杂质离子，以到达N +栅电极下方的一部分区域 通过使用具有对应于要形成DMOSFET的体漫射层的区域的开口和N +栅电极被激活的抗蚀剂膜。 此后，分别在P-体扩散层和N-漏极扩散层中形成N +源极扩散层和N +漏极扩散层。 由于不需要进行高温驱入工艺来将P型杂质离子引入到N +栅电极下面的区域，所以由杂质引起的阈值电压和栅极氧化膜的劣化的降低或变化 可以防止从N +栅电极扩散。 因此，提供了一种其上安装有DMOSFET的半导体器件，其具有降低的导通电阻，并且由于阈值电压的变化和高质量的栅氧化膜而抑制了寄生双极晶体管的激活。

公开(公告)号：US5406106A

公开(公告)日：1995-04-11

申请号：US76838

申请日：1993-06-15

申请人： Takehiro Hirai ,  Masahiro Nakatani ,  Mitsuo Tanaka ,  Akihiro Kanda

发明人： Takehiro Hirai ,  Masahiro Nakatani ,  Mitsuo Tanaka ,  Akihiro Kanda

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L29/51 ,  H01L27/02 ,  H01L27/04 ,  H01L29/68

CPC分类号： H01L29/513 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/518

摘要： A silicon oxide film as a dielectric film and a silicon nitride film or a polysilicon film as a protection film for the silicon oxide film are formed on a silicon substrate. After the two films are selectively etched to form contact holes of a bipolar transistor, a polysilicon film as a conductive film is laid on the entire substrate and selectively etched to form electrodes. In a MIS transistor, the protection film of the silicon nitride film serves as a gate insulator film and the protection film of the polysilicon film serves as a gate electrode. Accordingly, contamination to the gate insulator film at formation of contact holes of the bipolar transistor is prevented, and an excellent semiconductor with Bi-MOS structure is manufactured with low cost.

摘要翻译： 在硅衬底上形成作为电介质膜的氧化硅膜和作为氧化硅膜保护膜的氮化硅膜或多晶硅膜。 在选择性地蚀刻两个膜以形成双极晶体管的接触孔之后，将作为导电膜的多晶硅膜铺设在整个基板上并选择性地蚀刻以形成电极。 在MIS晶体管中，氮化硅膜的保护膜用作栅极绝缘膜，多晶硅膜的保护膜用作栅电极。 因此，防止了在形成双极晶体管的接触孔时对栅极绝缘膜的污染，并以低成本制造了具有Bi-MOS结构的优良半导体。

公开(公告)号：US5323054A

公开(公告)日：1994-06-21

申请号：US907470

申请日：1992-07-01

申请人： Akihiro Kanda ,  Mitsuo Tanaka ,  Takehiro Hirai ,  Masahiro Nakatani

发明人： Akihiro Kanda ,  Mitsuo Tanaka ,  Takehiro Hirai ,  Masahiro Nakatani

IPC分类号： H01L21/74 ,  H01L21/8226 ,  H01L27/082 ,  H01L29/165 ,  H01L29/700

CPC分类号： H01L21/8226 ,  H01L21/743 ,  H01L27/0826

摘要： In a a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same substrate, grooves that reach an n.sup.+ -type buried layer 5 serving as an emitter of the IIL and an n.sup.+ -type buried layer 4 serving as a collector of the vertical npn transistor are formed at the same time, and an oxide film 101 is formed only on the sidewall of each groove; in the grooves, n.sup.+ -type polycrystalline silicon films 103 and 102 are formed, which are made to serve as an emitter lead-out portion of the IIL and a collector wall of the vertical npn transistor, respectively; a p-type diffused layer 17 serving as an injector of the IIL and a p-type diffused layer 18 and p.sup.- -type diffused layer 12 serving as the base thereof are respectively so formed as to be adjoining to the oxide film 101 of the emitter lead-out portion of the IIL; and a p-type diffused layer 16 serving as the base of the vertical npn transistor is so formed as to be adjoining to the oxide film 101 of the collecter wall. The semiconductor device can achieve a smaller cell size, a decrease in parasitic capacitance and an increase in operating speed.

摘要翻译： 在具有垂直npn晶体管，集成在同一衬底上的垂直pnp晶体管和IIL的半导体器件中，到达用作IIL的发射极的n +型掩埋层5和n +型掩埋层4的沟槽 同时形成垂直npn晶体管的集电极，只在每个沟槽的侧壁上形成氧化膜101; 在凹槽中形成n +型多晶硅膜103和102，它们分别用作IIL的发射极引出部分和垂直npn晶体管的集电壁; 用作IIL的注射器的p型扩散层17和作为其基底的p型扩散层18和p型扩散层12分别形成为邻接于 发射极引出部分; 并且用作垂直npn晶体管的基极的p型扩散层16形成为与收集器壁的氧化物膜101相邻。 半导体器件可以实现更小的单元尺寸，寄生电容的减小和操作速度的增加。

公开(公告)号：US08653456B2

公开(公告)日：2014-02-18

申请号：US13577568

申请日：2011-02-09

申请人： Yasutaka Toyoda ,  Tomohiro Funakoshi ,  Takehiro Hirai

发明人： Yasutaka Toyoda ,  Tomohiro Funakoshi ,  Takehiro Hirai

IPC分类号： G01N23/00 ,  G21K7/00

CPC分类号： H01J37/28 ,  H01J37/244 ,  H01J2237/24495 ,  H01L22/12

摘要： It is an object of the present invention to provide a technique capable of accurately inspecting a circuit pattern in which the contrast of an observation image is not clear, like a circuit pattern having a multilayer structure. A pattern inspection method according to the present invention divides a circuit pattern using the brightness of a reflection electron image and associates the region in the reflection electron image belonging to each division with the region in a secondary electron image.

摘要翻译： 本发明的目的是提供一种能够精确地检查观察图像的对比度不清晰的电路图案的技术，如具有多层结构的电路图案。 根据本发明的图案检查方法使用反射电子图像的亮度来划分电路图案，并且将属于每个划分的反射电子图像中的区域与二次电子图像中的区域相关联。