公开(公告)号：US20240184468A1

公开(公告)日：2024-06-06

申请号：US18224477

申请日：2023-07-20

Applicant: SanDisk Technologies LLC

Inventor： Wei Cao ,  Xiang Yang

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes and is configured to identify at least one grouping of the memory cells to be programmed with a multi-pass programming operation. The control means is also configured to program the at least one grouping of the memory cells using the multi-pass programming operation. The control means is additionally configured to program the memory cells other than the at least one grouping of the memory cells in a full sequence programming operation.

公开(公告)号：US11972820B2

公开(公告)日：2024-04-30

申请号：US17898850

申请日：2022-08-30

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Dengtao Zhao ,  Xiang Yang

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102

Abstract: Memory cells are arranged as NAND strings to form a block divided into sub-blocks, and each NAND string includes a dummy memory cell connected to a dummy word line. Memory cells are programmed by applying programming pulses to a selected word line in a selected sub-block with program-verify performed between pulses. Unselected NAND strings are inhibited from programming by boosting channels of the unselected NAND strings in the selected sub-block from a positive pre-charge voltage to a boosted voltage. The pre-charging of the channels of unselected NAND strings is performed while lowering voltages at the end of program-verify by applying overdrive voltages to data word lines in a sub-block closer to the source line than the selected sub-block and lowering to a resting voltage a dummy word line between the sub-blocks prior to lowering to a resting voltage the data word lines in the sub-block closer to the source line.

公开(公告)号：US11972808B2

公开(公告)日：2024-04-30

申请号：US17666940

申请日：2022-02-08

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Xiang Yang

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3431 ,  H10B41/27 ,  H10B43/27

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings and configured to retain a threshold voltage. The memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes. A control means determines whether a downshift recovery trigger event has occurred in memory operations. In response to determining the downshift recovery trigger event has occurred, the control means inserts at least one of a predetermined idle time in the memory operations and a recovery pulse of a negative voltage to the drain-side select gate transistor of the memory holes of the strings for a predetermined pulse period of time during one of the memory operations.

公开(公告)号：US11961572B2

公开(公告)日：2024-04-16

申请号：US17511818

申请日：2021-10-27

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Abhijith Prakash ,  Shubhajit Mukherjee

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3404

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including at least one edge word line and other data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage corresponding to data states. The strings are organized in rows and a control means is coupled to the word lines and the strings and identifies the at least one edge word line. The control means programs the memory cells of the strings in particular ones of the rows and associated with the at least one edge word line to have an altered distribution of the threshold voltage for one or more of the data states compared to the memory cells of the strings not in particular ones of the rows and not associated with the at least one edge word line during a program operation.

公开(公告)号：US11894064B2

公开(公告)日：2024-02-06

申请号：US17583570

申请日：2022-01-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/102 ,  G11C16/26

Abstract: The memory device includes a block with a plurality of memory cells arranged in a plurality of data word lines, which are arranged in sub-blocks that are not separated from one another by physical joints or by dummy word lines. A controller is configured to erase the memory cells of a selected sub-block of the plurality of sub-blocks without erasing the memory cells of the unselected sub-blocks. The controller reads data of the edge one word lines of the unselected sub-blocks adjacent the selected sub-block and stores this data in a temporary location external of the block before erasing the memory cells of the selected sub-block. The controller then re-programs the data that is being temporarily stored back into the memory cells of the edge word lines of the unselected sub-blocks after erase of the selected sub-block is completed.

公开(公告)号：US20240029806A1

公开(公告)日：2024-01-25

申请号：US17872148

申请日：2022-07-25

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Peng Zhang ,  Xiang Yang ,  Yanli Zhang

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/08 ,  G11C16/24 ,  G11C16/0483

Abstract: In a non-volatile memory system that performs programming of selected memory cells (in coordination with pre-charging and boosting of channels for unselected memory cells) and program-verify to determine whether the programming was successful, the system transitions from program-verify to the next dose of programming by concurrently lowering a voltage applied to a selected word line and voltages applied to word lines on a first side of the selected word line at the conclusion of program-verify. Subsequent to lowering the voltage applied to the selected word line, the system successively lowers voltages applied to groups of one or more word lines on a second side of the selected word line at the conclusion of program-verify beginning with a group of one or more word lines immediately adjacent the selected word line and progressing to other groups of one or more word lines disposed increasingly remote from the selected word line.

公开(公告)号：US11837297B2

公开(公告)日：2023-12-05

申请号：US17344135

申请日：2021-06-10

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/16

CPC classification number: G11C16/3495 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3404 ,  G11C16/3445

Abstract: A method for dynamically adjusting an erase voltage level to be applied in a subsequent erase cycle, comprising: in a current erase cycle, initiating a current erase/verify loop by applying an initial stored erase voltage level according to an erase sequence in which each successive erase/verify loop is incremented by a pre-determined voltage amount, storing an erase/verify loop count, and determining whether the current erase cycle is complete according to a pass criterion. If the erase cycle is complete, a determination is made as to whether the stored erase/verify loop count equals a pre-defined threshold count. Further, if the stored count does not equal the pre-defined threshold count, the initial stored erase voltage level is adjusted such that, upon applying the adjusted erase voltage level in a subsequent erase cycle, an erase/verify loop count will now equal the pre-defined threshold count.

公开(公告)号：US20230386569A1

公开(公告)日：2023-11-30

申请号：US17825193

申请日：2022-05-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Muhammad Masuduzzaman ,  Jiacen Guo

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10

Abstract: A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the memory array, and (2) a zero voltage condition to one or more bit lines of the memory array such that less than half of the adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.

公开(公告)号：US11798625B2

公开(公告)日：2023-10-24

申请号：US17469016

申请日：2021-09-08

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Gerrit Jan Hemink

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  H10B43/10 ,  H10B43/27

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C11/5671 ,  H10B43/10 ,  H10B43/27

Abstract: An apparatus includes a control circuit configured to connect to first word lines of a first vertical sub-block and second word lines of a second vertical sub-block. The first vertical sub-block and the second vertical sub-block include memory cells connected in series in NAND strings, each NAND string including memory cells coupled to the first word lines in series with memory cells connected to the second word lines. The control circuit is configured to program or sense memory cells along a selected first word line of the first vertical sub-block while applying a first voltage to second word lines that are connected to programmed memory cells and applying a second voltage to second word lines that are connected to unprogrammed memory cells.

公开(公告)号：US11783903B2

公开(公告)日：2023-10-10

申请号：US17511966

申请日：2021-10-27

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Xiaochen Zhu

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/04 ,  G11C16/28 ,  G11C16/08 ,  G11C16/24 ,  G11C16/10

CPC classification number: G11C16/3445 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102 ,  G11C16/14 ,  G11C16/24 ,  G11C16/28 ,  G11C16/3404

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control means is coupled to the plurality of word lines and the strings. The control means is configured to apply a primary predetermined voltage to a primary location of the memory apparatus following an erase operation of the memory cells while simultaneously applying a secondary predetermined voltage being lower than the primary predetermined voltage to a secondary location of the memory apparatus and measuring a leak current at the primary location. The control means then determines the erase operation passed in response to the leak current measured not being greater than a predetermined leak threshold.