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    COMPARATOR SYSTEMS AND METHODS
    51.
    发明公开
    COMPARATOR SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20230283271A1

    公开(公告)日：2023-09-07

    申请号：US18157977

    申请日：2023-01-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Antonino Conte ,  Marco Ruta ,  Michelangelo Pisasale ,  Agatino Massimo Maccarrone ,  Francesco Tomaiuolo

    IPC: H03K5/24 ,  H03K3/03

    CPC classification number: H03K5/24 ,  H03K3/0315

    Abstract: A system a ring oscillator configured to produce a set of clock signals having the same clock period and a mutual time delay between respective clock signal edges. Comparator circuits are coupled to first and second input nodes and produce a set of comparison signals according to a respective sequence of comparison phases. A set of synchronization circuits is coupled to the ring oscillator and to the plurality of comparator circuits. The synchronization circuits allot, to each one of the comparator circuits, respective time windows for communication over respective communication lines of the comparison signals. The respective time windows are synchronized based on the clock signals. A multiplexer couples the respective communication lines to an output line to sequentially enable each of the comparator circuits to sequentially output respective comparison signals over the output line for the respective time windows thereby forming a composite comparison signal evolving over time.

    APPARATUS AND METHOD FOR A BANDGAP REFERENCE
    52.
    发明申请
    APPARATUS AND METHOD FOR A BANDGAP REFERENCE 有权

    公开(公告)号：US20210349489A1

    公开(公告)日：2021-11-11

    申请号：US16868799

    申请日：2020-05-07

    Applicant: STMicroelectronics S.r.l.

    Inventor： Antonino Conte

    IPC: G05F3/26

    Abstract: An apparatus includes a current mirror coupled to an output of an amplifier through control switches, a plurality of capacitors, each of which is coupled to a common node of a leg of the current mirror and a corresponding control switch, a first dipole coupled to a first input of an amplifier, a second dipole coupled to a second input of the amplifier, a third dipole coupled to an output of the apparatus configured to generate the bandgap reference voltage, and groups of switches coupled between the current mirror and the dipoles.

    Phase-change memory with selectors in BJT technology and differential-reading method thereof
    53.
    发明授权
    Phase-change memory with selectors in BJT technology and differential-reading method thereof 有权

    公开(公告)号：US10720210B2

    公开(公告)日：2020-07-21

    申请号：US16717652

    申请日：2019-12-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： Antonino Conte

    IPC: G11C7/06 ,  G11C7/08 ,  G11C13/00 ,  G11C5/14 ,  G11C7/12 ,  G11C7/18 ,  H01L45/00

    Abstract: A phase-change memory device includes a memory array including a first memory cell and a second memory cell, each comprising a phase-change element and a selector, connected respectively to a first local bitline and a second local bitline, which are in turn connected, respectively, to a first main bitline and a second main bitline. The parasitic capacitance of the main bitlines is precharged at a supply voltage. When the local bitlines are selected to access a respective logic datum stored in the phase-change element, the parasitic capacitance of the local bitlines is first charged using the charge previously stored in the parasitic capacitance of the main bitlines and then discharged through the respective phase-change elements. Reading of the logic datum is made by comparing the discharge times.

    Floating Boosted Pre-Charge Scheme for Sense Amplifiers
    54.
    发明申请
    Floating Boosted Pre-Charge Scheme for Sense Amplifiers 审中-公开

    公开(公告)号：US20200058360A1

    公开(公告)日：2020-02-20

    申请号：US16104001

    申请日：2018-08-16

    Applicant: STMicroelectronics S.r.l.

    Inventor： Antonino Conte ,  Loredana Chiaramonte ,  Anna Rita Maria Lipani

    IPC: G11C16/28 ,  G11C16/04 ,  G11C16/24

    Abstract: A sense structure includes: a sense amplifier core configured to compare a measurement current with a reference current; a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load; a switch coupled between a bias voltage node and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between a second terminal of the local capacitor and a reference terminal; and a control circuit coupled to a control terminal of the first transistor, the control circuit configured to disconnect the local capacitor from the reference terminal to produce a voltage overshoot in the control terminal of the cascode transistor, and after disconnecting the local capacitor from the reference terminal, limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor.

    VOLTAGE REGULATOR WITH IMPROVED ELECTRICAL PROPERTIES AND CORRESPONDING CONTROL METHOD
    56.
    发明申请
    VOLTAGE REGULATOR WITH IMPROVED ELECTRICAL PROPERTIES AND CORRESPONDING CONTROL METHOD 审中-公开

    公开(公告)号：US20170248981A1

    公开(公告)日：2017-08-31

    申请号：US15596895

    申请日：2017-05-16

    Applicant: STMicroelectronics S.r.l.

    Inventor： Antonino Conte ,  Carmelo Paolino

    IPC: G05F1/575 ,  G05F1/56 ,  H03F1/34 ,  H03F1/42 ,  H02M3/07 ,  H03F3/45

    CPC classification number: G05F1/575 ,  G05F1/56 ,  H02M3/07 ,  H03F1/34 ,  H03F1/42 ,  H03F3/45

    Abstract: A voltage-regulator device includes an error-amplifier stage configured to receive a first reference voltage and a feedback voltage, an output amplifier stage coupled to the error-amplifier stage and configured to generate an output voltage related to the first reference voltage by an amplification factor, and a feedback stage configured to generate the feedback voltage. A compensation stage is configured to implement a second feedback loop, and cause, in response to a variation of the output voltage, a corresponding variation of a first biasing voltage for the output amplifier stage. The compensation stage includes a coupling-capacitor element coupled between the output amplifier stage and a first internal node, and a driving module coupled between the first internal node, and the output amplifier stage and configured to generate a compensation voltage for driving the output amplifier stage.

    HIGH PERFORMANCE DIGITAL TO ANALOG CONVERTER
    60.
    发明申请
    HIGH PERFORMANCE DIGITAL TO ANALOG CONVERTER 有权
    高性能数字到模拟转换器

    公开(公告)号：US20150263758A1

    公开(公告)日：2015-09-17

    申请号：US14638246

    申请日：2015-03-04

    Applicant: STMICROELECTRONICS S.r.l.

    Inventor： Antonino Conte ,  Maria Giaquinta

    IPC: H03M1/66 ,  G11C16/06

    CPC classification number: G11C16/06 ,  H03F1/34 ,  H03F3/347 ,  H03F3/45 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2200/156 ,  H03F2200/375 ,  H03F2200/453 ,  H03F2203/45101 ,  H03F2203/45332 ,  H03F2203/45514 ,  H03F2203/45546 ,  H03F2203/45632 ,  H03M1/661

    Abstract: A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.

    Abstract translation: 数模转换器（DAC）可以包括提供第一模拟值的转换块。 DAC还可以包括用于接收第一模拟值并提供由放大因子放大的第二模拟值的放大块。 放大块可以包括用于接收第一模拟值的第一输入端，第二输入端和用于提供第二模拟值的输出端。 放大块还可以包括第一电容元件和第二电容元件。 第一和第二电容元件可以确定放大系数。 放大块还可以包括用于在第二电容元件的第一端子处恢复电荷的控制单元，并且基于该第二模拟值。

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