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    CAPACITOR COMPONENT
    52.
    发明公开
    CAPACITOR COMPONENT 审中-公开

    公开(公告)号：US20230197347A1

    公开(公告)日：2023-06-22

    申请号：US17712424

    申请日：2022-04-04

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Sang Jong LEE ,  Su Bong JANG ,  Min Cheol PARK ,  Tae Ho YUN ,  Han KIM

    IPC: H01G4/248 ,  H01G4/232 ,  H01G4/30

    CPC classification number: H01G4/248 ,  H01G4/232 ,  H01G4/30

    Abstract: A capacitor component includes a body having first surface and second surfaces opposing each other and including through-holes penetrating through the first surface and the second surface, a first electrode covering an inner wall of each of the plurality of through-holes, a first common electrode covering the first surface and connected to the first electrode, a dielectric layer surrounded by the first electrode in the through-hole, a second electrode surrounded by the dielectric layer in the through-hole, a second common electrode layer covering the second surface and connected to the second electrode, a first external electrode disposed on at least one of a plurality of side surfaces of the body and connected to the first common electrode layer, and a second external electrode disposed on at least one of the plurality of side surfaces of the body and connected to the second common electrode layer.

    FAN-OUT SEMICONDUCTOR PACKAGE
    55.
    发明申请
    FAN-OUT SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20190326223A1

    公开(公告)日：2019-10-24

    申请号：US16171114

    申请日：2018-10-25

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Yun Tae LEE ,  Eun Jung JO ,  Han KIM

    IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18 ,  H01L25/065

    Abstract: A fan-out semiconductor package includes a core member having a first through-hole and including wiring layers; a first semiconductor chip disposed in the first through-hole and having first connection pads formed on a lower side of the first semiconductor chip; a first encapsulant covering the core member and the first semiconductor chip; a connection member disposed below the core member and the first semiconductor chip and including redistribution layers; a first stack chip disposed on the first encapsulant and electrically connected to the wiring layers through a first connection conductor; and a second encapsulant disposed on the first encapsulant and covering the first stack chip. The first semiconductor chip includes DRAM and/or a controller, the first stack chip includes a stack type NAND flash, and the first connection pads of the first semiconductor chip are electrically connected to the wiring layers through the redistribution layers.

    SEMICONDUCTOR PACKAGE
    56.
    发明申请
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20190244885A1

    公开(公告)日：2019-08-08

    申请号：US16105289

    申请日：2018-08-20

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Eun Jin KIM ,  Han KIM

    IPC: H01L23/498 ,  H01L23/31 ,  H01L23/043

    Abstract: A semiconductor package includes a connection member having a first surface and a second surface disposed to oppose each other and including an insulating member having a plurality of insulating layers and a plurality of redistribution layers disposed on the plurality of insulating layers, respectively; a semiconductor chip disposed on the first surface of the connection member and having connection pads electrically connected to the plurality of redistribution layers; and an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, wherein at least one of the plurality of redistribution layers includes a dummy electrode pattern in which a plurality of holes are arranged, and each of the plurality of holes has a shape including a plurality of protruding regions that protrude externally from different positions.

    SEMICONDUCTOR PACKAGE
    58.
    发明申请
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20190189579A1

    公开(公告)日：2019-06-20

    申请号：US15965590

    申请日：2018-04-27

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Seok Hwan KIM ,  Han KIM ,  Kyung Ho LEE ,  Kyung Moon JUNG

    IPC: H01L23/00 ,  H01L23/28 ,  H01L23/538 ,  H01L23/498

    Abstract: A semiconductor package includes: a connection member having a first surface and a second surface opposing each other in a stacking direction of the semiconductor package and including an insulating member and a redistribution layer formed on the insulating member and having a redistribution via; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; a passivation layer disposed on the second surface of the connection member; UBM pads disposed on the passivation layer and overlapping the redistribution vias in the stacking direction; and UBM vias connecting the UBM pads to the redistribution layer through the passivation layer, not overlapping the redistribution vias with respect to the stacking direction, and having a non-circular cross section.

    FAN-OUT SEMICONDUCTOR PACKAGE
    59.
    发明申请
    FAN-OUT SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20190172793A1

    公开(公告)日：2019-06-06

    申请号：US15923308

    申请日：2018-03-16

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Han KIM ,  Sung Han KIM ,  Seok Hwan KIM

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

    Abstract: A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; a passivation layer disposed on the connection member and having openings exposing at least portions of the redistribution layer; metal members disposed in the openings of the passivation layer and connected to the exposed redistribution layer; and electrical connection structures disposed on the passivation layer and connected to the metal members, wherein the electrical connection structures have heights hierarchically differentiated from one another depending on sizes of the metal members.

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