公开(公告)号：US20240014086A1

公开(公告)日：2024-01-11

申请号：US18135541

申请日：2023-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokgeun Ahn ,  Seokhyun Lee ,  Hwanyoung Choi

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/3114 ,  H01L25/0657 ,  H01L23/49838 ,  H01L21/563 ,  H01L24/05 ,  H01L23/5226 ,  H01L24/16 ,  H01L2224/04105 ,  H01L2225/06544 ,  H01L2224/05009 ,  H01L2224/16227 ,  H01L2924/182

Abstract: A semiconductor package includes: a substrate; a circuit layer disposed on a lower surface of the substrate, the circuit layer including an interconnection structure; a first redistribution structure disposed adjacent to the circuit layer, the first redistribution structure including a first redistribution layer; a connection structure including a first connection via electrically connected to the first redistribution layer, a second connection via electrically connected to the interconnection structure, and a connection interconnection interconnecting the first and second connection vias; a semiconductor chip disposed below the first redistribution structure, and electrically connected to the first redistribution layer; a first vertical connection structure disposed on a lower surface of the circuit layer; a second vertical connection structure disposed on a lower surface of the connection structure; and a second redistribution structure disposed below the semiconductor chip and the first and second vertical connection structures.

公开(公告)号：US11837551B2

公开(公告)日：2023-12-05

申请号：US17215517

申请日：2021-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Seokhyun Lee ,  Gwangjae Jeon

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L23/5386 ,  H01L24/14

Abstract: A semiconductor package includes a redistribution substrate having a semiconductor chip mounted on a top surface thereof with and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate includes a first redistribution pattern on a bottom surface of the connection terminal and comprising a first via and a first interconnection on the first via, a pad pattern between the first redistribution pattern and the connection terminal and comprising a pad via and a pad on the pad via, and a second redistribution pattern between the first redistribution pattern and the pad pattern and comprising a second via and a second interconnection on the second via with a recess region where a portion of a top surface of the second interconnection is recessed. A bottom surface of the recess region is located at a lower level than a topmost surface of the second interconnection.

公开(公告)号：US11626393B2

公开(公告)日：2023-04-11

申请号：US17179470

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung Lim Suk ,  Seokhyun Lee

IPC: H01L21/44 ,  H01L25/10 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.

公开(公告)号：US20230056041A1

公开(公告)日：2023-02-23

申请号：US17706978

申请日：2022-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Jongyoun Kim ,  Seokhyun Lee ,  Minjung Kim

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes: a base substrate including a lower redistribution layer; a lower semiconductor chip including a first active surface and on the base substrate; an upper semiconductor chip including a second active surface on the lower semiconductor chip and having an area larger than that of the lower semiconductor chip; an intermediate connection member including an upper redistribution layer on the second active surface of the upper semiconductor chip between the lower and upper semiconductor chips; a plurality of vertical interconnectors disposed around the lower semiconductor chip on the base substrate and connecting the lower redistribution layer and the upper redistribution layer; and a molding portion on the base substrate and including a first portion surrounding the lower semiconductor chip and the vertical interconnectors, and a second portion extending upwardly from the first portion and on side surfaces of the upper semiconductor chip and the intermediate connection member.

公开(公告)号：US20220224927A1

公开(公告)日：2022-07-14

申请号：US17575414

申请日：2022-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Taesung Kim

IPC: H04N19/423 ,  H04N19/91 ,  H04N19/137 ,  H04N19/159 ,  H04N19/593 ,  H04N19/186

Abstract: A video decoding apparatus includes a first buffer storing input data received from an entropy decoder, a first motion compensation processor extracting motion compensation reference data based on the input data, and store the motion compensation reference data in a pixel cache, a second buffer, and a controller. The input data comprises one of first data including motion information and second data including intra prediction information. The controller controls the second buffer to store the motion compensation reference data stored in the pixel cache when the input data is the first data, and controls the second buffer to store the second data stored in the first buffer when the input data is the second data.

公开(公告)号：US11348864B2

公开(公告)日：2022-05-31

申请号：US16885546

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Gwangjae Jeon

IPC: H01L23/498

Abstract: Disclosed are redistribution substrates and semiconductor packages including the same. For example, a redistribution substrate including a dielectric pattern, and a first redistribution pattern in the dielectric pattern is provided. The first redistribution pattern may include: a first via part having a first via seed pattern and a first via conductive pattern on the first via seed pattern, and a first wiring part having a first wiring seed pattern and a first wiring conductive pattern, the first wiring part being disposed on the first via part and having a horizontal width that is different from a horizontal width of the first via part. Additionally, the first wiring seed pattern may cover a bottom surface and a sidewall surface of the first wiring conductive pattern, and the first via conductive pattern is directly connected to the first wiring conductive pattern.

公开(公告)号：US20220077048A1

公开(公告)日：2022-03-10

申请号：US17329256

申请日：2021-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung Lim Suk ,  Keung Beum Kim ,  Dongkyu Kim ,  Minjung Kim ,  Seokhyun Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/10

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

公开(公告)号：US11018108B2

公开(公告)日：2021-05-25

申请号：US16914384

申请日：2020-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youn Ji Min ,  Seokhyun Lee ,  Jongyoun Kim ,  Kyoung Lim Suk ,  SeokWon Lee

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L25/10 ,  H01L21/683 ,  H01L23/498

Abstract: A semiconductor package includes: a redistribution substrate; a semiconductor chip on the redistribution substrate; and an external terminal on a bottom surface of the redistribution substrate, wherein the redistribution substrate comprises: a first insulating layer including a first opening; a second insulating layer on the first insulating layer and including a second opening, wherein the second opening is positioned in the first opening in a plan view; a first barrier metal layer disposed along a sidewall of the first opening and along a sidewall of the second opening; a first redistribution conductive pattern on the first barrier metal layer; a third insulating layer on a bottom surface of the first insulating layer; and a pad penetrating the third insulating layer and electrically connecting to the first redistribution conductive pattern, wherein the external terminal is provided on the pad, wherein the second insulating layer at least partially covers a chip pad of the semiconductor chip, and the second opening at least partially exposes the chip pad, wherein, inside the second insulating layer, the first barrier metal layer is in contact with the chip pad through the second opening, and wherein the first redistribution conductive pattern has a surface roughness including protrusions extending in a range of from about 0.01 μm to about 0.5 μm, and the first insulating layer has a surface roughness smaller than the surface roughness of the first redistribution conductive pattern.

公开(公告)号：US20210066560A1

公开(公告)日：2021-03-04

申请号：US16860255

申请日：2020-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dahye Kim ,  Seokhyun Lee ,  Jungho Park

IPC: H01L33/62 ,  H01L33/56 ,  H01L33/48

Abstract: A display module package includes a semiconductor chip, a wiring member disposed on the semiconductor chip, including an insulating layer and a wiring layer, and contacting at least a portion of the semiconductor chip, a light emitting device array disposed on the wiring member and including a plurality of light emitting devices disposed on one surface, wherein the wiring member is between the semiconductor chip and the light emitting device, and a molding member disposed on the wiring member, sealing part of the light emitting device array, and having an opening for exposing the plurality of light emitting devices.

公开(公告)号：US10930625B2

公开(公告)日：2021-02-23

申请号：US16430426

申请日：2019-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung Lim Suk ,  Seokhyun Lee

IPC: H01L25/10 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.