公开(公告)号：US10700078B1

公开(公告)日：2020-06-30

申请号：US16278488

申请日：2019-02-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Masatoshi Nishikawa ,  Yanli Zhang

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11529 ,  H01L27/11519 ,  H01L27/11575 ,  H01L27/11578 ,  H01L21/28

Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.

公开(公告)号：US10692884B2

公开(公告)日：2020-06-23

申请号：US16138001

申请日：2018-09-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Kiyohiko Sakakibara ,  Shinsuke Yada

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/11543 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L21/28

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, drain-select-level gate electrodes located over the alternating stack, memory openings extending through the alternating stack and a respective one of the drain-select-level gate electrodes, and memory opening fill structures located in the memory openings. The memory opening fill structures can have a stepped profile to provide a smaller lateral dimension at the level of the drain-select-level gate electrodes than within the alternating stack. Each of the drain-select-level gate electrodes includes a planar portion having two sets of vertical sidewall segments, and a set of cylindrical portions vertically protruding upward from the planar portion and laterally surrounding a respective one of the memory opening fill structures. The memory opening fill structures can be formed on-pitch as a two-dimensional array.

公开(公告)号：US20190326313A1

公开(公告)日：2019-10-24

申请号：US16024048

申请日：2018-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Kiyohiko Sakakibara ,  Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kenji Sugiura

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/28

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.

公开(公告)号：US20190280003A1

公开(公告)日：2019-09-12

申请号：US16020817

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kensuke Yamaguchi ,  James Kai ,  Zhixin Cui ,  Murshed Chowdhury ,  Johann Alsmeier ,  Tong Zhang

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11526 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522

Abstract: Multiple tier structures are stacked over a substrate. Each tier structure includes an alternating stack of insulating layers and sacrificial material layers and a retro-stepped dielectric material portion overlying the alternating stack. Multiple types of openings are formed concurrently during formation of each tier structure. Openings concurrently formed through each tier structure can include at least two types of openings that may be selected from through-tier memory openings, through-tier support openings, and through-tier staircase-region openings. Each through-tier opening is filled with a respective through-tier sacrificial opening fill structure. Stacks of through-tier sacrificial opening fill structures can be removed in stages to form various device components, which include memory stack structures, support pillar structures, and staircase-region contact via structures. The sacrificial material layers are replaced with electrically conductive layers, which are laterally electrically isolated from the staircase-region contact via structures by annular insulating spacers.

公开(公告)号：US10355009B1

公开(公告)日：2019-07-16

申请号：US16020637

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Zhixin Cui ,  Murshed Chowdhury ,  Johann Alsmeier ,  Tong Zhang

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/768 ,  H01L21/8239 ,  H01L21/822

Abstract: A first-tier structure including a first alternating stack of first insulating layers and first spacer material layers is formed over a substrate. First-tier memory openings and at least one type of first-tier contact openings can be formed simultaneously employing a same anisotropic etch process. The first-tier contact openings formed over stepped surfaces of the first alternating stack may extend through the first alternating stack, or may stop on the stepped surfaces. Sacrificial first-tier opening fill portions are formed in the first-tier openings, and a second-tier structure can be formed over the first-tier structure. Memory openings including volumes of the first-tier memory openings are formed through the multi-tier structure, and memory stack structures are formed in the memory openings. Various contact openings are formed through the multi-tier structure, and various contact via structures are formed in the contact openings.

公开(公告)号：US09960181B1

公开(公告)日：2018-05-01

申请号：US15488924

申请日：2017-04-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Masahiro Wada

IPC: H01L23/522 ,  H01L27/115 ,  H01L27/11582 ,  H01L23/528 ,  H01L21/28 ,  H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L21/0273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/7889 ,  H01L29/7926

Abstract: Contact areas for three-dimensional memory devices including multiple vertically stacked tier structures can be reduced by overlapping stepped terraces of the tier structures. Sacrificial via structures laterally surrounded by a respective insulating spacer can be formed through an overlying tier structure in the stepped terrace region thereof. After formation of memory stack structures, the sacrificial via structures can be removed to provide first upper via cavities. An isotropic etch can be performed to extend the first upper via cavities to top surfaces of underlying first electrically conductive layers in an underlying tier structure while forming second upper via cavities extending to second electrically conductive layers in the overlying tier structure. First contact via structures extending through the terrace region of the overlying tier structure can provide electrical contact to the first electrically conductive layers, and second contact via structure can be formed in the second upper via cavities.