Error correcting circuit and disk storage device for detecting and correcting insertion and/or deletion errors
    51.
    发明授权
    Error correcting circuit and disk storage device for detecting and correcting insertion and/or deletion errors 失效
    错误纠正电路和磁盘存储设备,用于检测和纠正插入和/或删除错误

    公开(公告)号:US08386888B2

    公开(公告)日:2013-02-26

    申请号:US12849722

    申请日:2010-08-03

    申请人: Toshio Ito

    发明人: Toshio Ito

    IPC分类号: G11C29/00

    摘要: An error correcting circuit includes a marker decoder for sampling 2-bit markers from a data string and, from sample values of the 2-bit markers, determine whether there is an occurrence of an error on the 2-bit markers, of an insertion error, or of a deletion error. The circuit also includes an error corrector for performing an error correction on the data string received from the marker decoder by using an error correcting code in the data string. When either one of the insertion error and the deletion error is determined to have occurred, the marker decoder can perform another error correction on the either one of the insertion error and the deletion error, and output the data string from which the 2-bit markers are removed.

    摘要翻译: 误差校正电路包括用于从数据串中采样2位标记的标记解码器,并且从2位标记的采样值确定是否存在2位标记上的错误的插入误差 ,或删除错误。 电路还包括误差校正器,用于通过使用数据串中的纠错码对从标记解码器接收的数据串执行纠错。 当插入错误和删除错误中的任一个被确定为已经发生时,标记解码器可以对插入错误和删除错误中的任一个执行另一个错误校正,并且输出2位标记 被删除。

    Encoding device, decoding device, encoding/decoding device, and recording/reproducing device
    52.
    发明授权
    Encoding device, decoding device, encoding/decoding device, and recording/reproducing device 失效
    编码装置,解码装置,编码/解码装置和记录/再现装置

    公开(公告)号:US08151162B2

    公开(公告)日:2012-04-03

    申请号:US12276958

    申请日:2008-11-24

    IPC分类号: H03M13/00

    摘要: An error correction device error corrects without increasing in circuit scale. An encoder, includes: a first ECC encoder which interleaves a data string into n (n≧2) blocks of data strings at every m (m≧2) bits, and adds the error correction code parity; a parity encoder which creates a parity bit at every plurality of bits of the error correction code word, and adds the parity bit to said error correction code word; and a second ECC encoder, which generates a second error correction encoding, which is a linear encoding using iterative decoding. Concatenated type encoded data, where a parity bit is added to every plurality of bits, is created, so an increase of circuit scale can be prevented even if a data string is interleaved into a plurality of blocks and error correction code parity is generated.

    摘要翻译: 错误纠正装置的错误在电路规模上没有增加。 一种编码器,包括:第一ECC编码器,每m(m≥2)位将数据串交织成n(n≥2)个数据串块,并加上纠错码奇偶校验; 奇偶校验编码器,其在所述纠错码字的每多个位产生奇偶校验位,并将所述奇偶校验位加到所述纠错码字; 以及第二ECC编码器,其生成使用迭代解码的线性编码的第二纠错编码。 创建了对每个多个比特添加奇偶校验位的级联型编码数据,因此即使将数据串交错为多个块并产生纠错码奇偶校验,也可以防止电路规模的增加。

    Centrifugal compressor and dry gas seal system for use in it
    53.
    发明授权
    Centrifugal compressor and dry gas seal system for use in it 有权
    离心式压缩机和干气密封系统用于其中

    公开(公告)号:US07854587B2

    公开(公告)日:2010-12-21

    申请号:US11635551

    申请日:2006-12-08

    IPC分类号: F01D11/06 F04D29/08

    CPC分类号: F01D11/04 F04D29/124

    摘要: The present invention relates to a centrifugal compressor using a dry gas seal system for protecting seal means. A multistage centrifugal compressor has primary dry gas seal means for preventing leakage of working gas from a machine inner side, and secondary dry gas seal means for backing up the first dry gas seal means. A seal gas line for introducing the gas leaked from the first and second dry gas seal means to the outside of the machine is installed between the primary dry gas seal means and the secondary dry gas seal means. The gas seal line has an orifice and a check valve, and buffer means is installed between the orifice and the check valve.

    摘要翻译: 本发明涉及一种使用干燥气体密封系统来保护密封装置的离心式压缩机。 多级离心压缩机具有用于防止工作气体从机器内侧泄漏的主要干燥气体密封装置和用于支撑第一干燥气体密封装置的二次干燥气体密封装置。 用于将从第一和第二干燥气体密封装置泄漏的气体引入机器外部的密封气体管线安装在主干燥气体密封装置和次级干燥气体密封装置之间。 气体密封线具有孔口和止回阀,缓冲装置安装在孔口和止回阀之间。

    Error correction apparatus
    54.
    发明授权
    Error correction apparatus 有权
    纠错装置

    公开(公告)号:US07793197B2

    公开(公告)日:2010-09-07

    申请号:US11509282

    申请日:2006-08-24

    IPC分类号: H03M13/00

    摘要: One set of syndromes is calculated from a first data string from among a plurality thereof including at least 2t+1 pieces of symbols as a parity string, and coefficients of an error locator polynomial from the one set of the syndromes. Whether or not a correction is successful is judged by using the coefficients of the error locator polynomial and the same calculation is performed for a second data string if a correction failure is judged. Contrarily, if a correction success is judged, an error of the first data string is corrected by using the aforementioned set of the syndromes and the coefficients of the error locator polynomial.

    摘要翻译: 从包括至少2t + 1个符号作为奇偶校验串的多个第一数据串中计算一组综合征,以及来自一组综合征的误差定位多项式的系数。 通过使用误差定位多项式的系数来判断校正是否成功,如果判断出校正失败,则对第二数据串执行相同的计算。 相反,如果判断校正成功,则通过使用上述的校正子集和误差定位多项式的系数来校正第一数据串的错误。

    MTR encoding method, MTR decoding method, MTR encoder, MTR decoder, and magnetic recording device
    55.
    发明授权
    MTR encoding method, MTR decoding method, MTR encoder, MTR decoder, and magnetic recording device 失效
    MTR编码方法,MTR解码方法,MTR编码器,MTR解码器和磁记录装置

    公开(公告)号:US07388523B2

    公开(公告)日:2008-06-17

    申请号:US11484933

    申请日:2006-07-12

    IPC分类号: H03M5/00

    CPC分类号: H03M5/145

    摘要: An MTR encoder includes convolution units that perform convolution of input data using additional bits, MTR encoding units that MTR-encode data obtained by the convolution units, RDS calculating units and on-bit sequence checking units that calculate RDSs and counts the number of sequential on-bits of the data MTR-encoded by the MTR encoding units, respectively, and a selecting unit that selects optimum data based on the RDSs and the number of sequential on-bits.

    摘要翻译: MTR编码器包括使用附加位执行输入数据的卷积的卷积单元,对由卷积单元获得的数据进行MTR编码的MTR编码单元,RDS计算单元和计算RDS的计数单元,并对序列数进行计数 分别由MTR编码单元MTR编码的数据的一行和选择单元,其基于RDS和顺序导通位数选择最佳数据。

    Encoder and decoder using run-length-limited code
    56.
    发明授权
    Encoder and decoder using run-length-limited code 失效
    编码器和解码器使用运行长度限制代码

    公开(公告)号:US07385533B2

    公开(公告)日:2008-06-10

    申请号:US11484003

    申请日:2006-07-10

    IPC分类号: H03M5/00

    CPC分类号: H03M5/145

    摘要: When a zero run, which violating G constraint of a run-length-limited (RLL) code, is detected from the data stored in a first input register 1111 and a second input register 1112, bits before and after the zero run is transferred to a temporary register 1150 via a bus for zero run removal 1130 to be combined to each other. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit.

    摘要翻译: 当从存储在第一输入寄存器1111和第二输入寄存器1112中的数据检测违反游程长度限制(RLL)代码的G约束的零运行时,将零运行之前和之后的位传送到 一个临时寄存器1150通过总线进行零运行移除1130以彼此组合。 因此,通过有效地利用总线传送的机制,可以简化电路,从而实现小电路。

    Recording and reproducing apparatus
    57.
    发明授权
    Recording and reproducing apparatus 有权
    记录和再现设备

    公开(公告)号:US07138931B2

    公开(公告)日:2006-11-21

    申请号:US10982610

    申请日:2004-11-05

    IPC分类号: H03M7/00

    CPC分类号: H03M5/145 G11B20/1426

    摘要: A recording and reproducing apparatus includes an RLL encoder that encodes an information bit string to a code bit string and a RLL decoder that decodes the code bit string to the information bit string. The RLL encoder encodes the information bit string to the code bit string of a run-length-limited code at a high encoding rate satisfying a plurality of conditions of constraint regarding a string of successive zeros. The RLL decoder decodes the code bit string encoded by the RLL encoder to the information bit string.

    摘要翻译: 记录和再现装置包括将信息位串编码为码位串的RLL编码器和将码位串解码为信息位串的RLL解码器。 RLL编码器以满足关于连续零串的多个约束条件的高编码率将信息位串编码为游程长度受限码的码位串。 RLL解码器将由RLL编码器编码的码位串解码为信息位串。

    Semiconductor memory device
    58.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号:US20060076594A1

    公开(公告)日:2006-04-13

    申请号:US11155609

    申请日:2005-06-20

    申请人: Toshio Ito

    发明人: Toshio Ito

    IPC分类号: H01L29/94

    摘要: The present invention provides a semiconductor memory device which comprises an interlayer insulating film formed on a semiconductor substrate, a contact plug formed in the interlayer insulating film and having one end electrically connected to the semiconductor substrate, a ferroelectric capacitor formed on the interlayer insulating film and comprising a first electrode, a ferroelectric film and a second electrode electrically connected to the other end of the contact plug, an insulating film which covers the ferroelectric capacitor and has an opening that exposes the first electrode, and a wiring film which covers the ferroelectric capacitor and the insulating film and is electrically connected to the first electrode exposed through the opening and which consists of a material having conductivity and even a hydrogen diffusion preventing function.

    摘要翻译: 本发明提供一种半导体存储器件,其包括形成在半导体衬底上的层间绝缘膜,形成在层间绝缘膜中并具有与半导体衬底电连接的一端的接触插塞,形成在层间绝缘膜上的铁电电容器和 包括电连接到所述接触插塞的另一端的第一电极,铁电体膜和第二电极,覆盖所述铁电电容器并具有暴露所述第一电极的开口的绝缘膜,以及覆盖所述铁电电容器的布线膜 和绝缘膜,并且电连接到通过开口暴露的第一电极,并且由具有导电性和甚至氢扩散防止功能的材料构成。

    Semiconductor optical amplifier characteristic evaluation method and apparatus
    59.
    发明授权
    Semiconductor optical amplifier characteristic evaluation method and apparatus 失效
    半导体光放大器特性评估方法及装置

    公开(公告)号:US06728025B2

    公开(公告)日:2004-04-27

    申请号:US10263233

    申请日:2002-10-02

    IPC分类号: H01S300

    CPC分类号: H04B10/0731

    摘要: In an SOA characteristic evaluation method, the current is supplied to an SOA. An optical output generated by the SOA that have received the current is measured. Transmission light obtained by transmitting the optical output through a wavelength filter and/or a polarizer is measured. The characteristic of the SOA is evaluated on the basis of the measurement result of the optical output and the measurement result of the transmission light without using an optical input to the SOA. An SOA characteristic evaluation apparatus is also disclosed.

    摘要翻译: 在SOA特性评估方法中,将电流提供给SOA。 测量已经接收到电流的由SOA生成的光输出。 测量通过波长滤波器和/或偏振器透射光输出而获得的透射光。 基于光输出的测量结果和传输光的测量结果,不对SOA进行光输入来评估SOA的特性。 还公开了SOA特性评估装置。