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公开(公告)号：US06384630B2
公开(公告)日：2002-05-07
申请号：US09760231
申请日：2001-01-12
申请人： Richard G. Cliff , Srinivas T. Reddy , Kerry Veenstra , Andreas Papaliolios , Chiakang Sung , Richard Shaw Terrill , Rina Raman , Robert Richard Noel Bielby
发明人： Richard G. Cliff , Srinivas T. Reddy , Kerry Veenstra , Andreas Papaliolios , Chiakang Sung , Richard Shaw Terrill , Rina Raman , Robert Richard Noel Bielby
IPC分类号： H03K19177
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/1774 , H03K19/17744 , H03K19/17748
摘要： Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.
摘要翻译： 可编程逻辑阵列器件由网络中的编程设备编程，这些器件可以利用任何大小或复杂度的程序来编程任何数量的这种逻辑器件。 编程数据和控制的源可以是微处理器或一个或多个串行EPROM，一个EPROM配备有时钟电路。 可以使用几个并行数据流来加速编程操作。 可以提供具有可编程可变速度的时钟电路以便于具有不同速度特性的编程逻辑器件。 编程协议可以包括在每个编程数据传输之后从逻辑设备到编程数据源的确认，使得源可以以逻辑设备能够接受该数据的速度自动发送编程数据。
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公开(公告)号：US5543730A
公开(公告)日：1996-08-06
申请号：US442801
申请日：1995-05-17
申请人： Richard G. Cliff , Srinivas T. Reddy , Kerry Veenstra , Andreas Papaliolios , Chiakang Sung , Richard S. Terrill , Rina Raman , Robert R. N. Bielby
发明人： Richard G. Cliff , Srinivas T. Reddy , Kerry Veenstra , Andreas Papaliolios , Chiakang Sung , Richard S. Terrill , Rina Raman , Robert R. N. Bielby
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/1774 , H03K19/17748
摘要： Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgement from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.
摘要翻译： 可编程逻辑阵列器件由网络中的编程设备编程，这些器件可以利用任何大小或复杂度的程序来编程任何数量的这种逻辑器件。 编程数据和控制的源可以是微处理器或一个或多个串行EPROM，一个EPROM配备有时钟电路。 可以使用几个并行数据流来加速编程操作。 可以提供具有可编程可变速度的时钟电路以便于具有不同速度特性的编程逻辑器件。 编程协议可以包括在每个编程数据传输之后从逻辑设备到编程数据源的确认，使得源可以以逻辑设备能够接受该数据的速度自动发送编程数据。
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公开(公告)号：US5498975A
公开(公告)日：1996-03-12
申请号：US147601
申请日：1993-11-04
申请人： Richard G. Cliff , Rina Raman , Srinivas T. Reddy
发明人： Richard G. Cliff , Rina Raman , Srinivas T. Reddy
IPC分类号： H01L21/82 , G06F11/20 , H03K19/003 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/00392
摘要： An improved architecture and method of operation for providing redundancy in programmable logic devices. Spare columns or rows of logic blocks 115 and switch boxes 140 are employed to replace columns or rows of logic blocks containing one or more defective logic blocks. Associated logic enable the device to bypass a column or row of logic blocks 115 containing one or more defective logic blocks 115 and to switch in a spare column or row of defect-free logic blocks 115 as replacement.
摘要翻译： 用于在可编程逻辑器件中提供冗余的改进的架构和操作方法。 逻辑块115和开关盒140的备用列或行被用于替代包含一个或多个有缺陷逻辑块的逻辑块的列或行。 相关联的逻辑使得设备绕过包含一个或多个有缺陷逻辑块115的逻辑块115的列或行，并且作为替换来切换备用列或无缺陷逻辑块115。
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54.发明授权Programmable logic device memory array circuit having combinable single-port memory arrays 有权具有可组合单端口存储器阵列的可编程逻辑器件存储器阵列电路公开(公告)号：US06191998B1
公开(公告)日：2001-02-20
申请号：US09452627
申请日：1999-12-01
IPC分类号： G11C800
CPC分类号： G11C7/10 , G11C7/1075 , G11C8/16 , G11C11/005
摘要： A programmable logic device memory array circuit is provided that contains a pair of associated combinable single-port memory arrays. The memory array circuit may have a variable depth and width. The combinable single-port memory arrays may be operated independently if desired. Alternatively, a pair of the combinable single-port memory arrays can be combined to form a dual-port memory array. When the single-port memory arrays are combined to form a dual-port memory array, circuitry from a first of the combinable single-port memory arrays is used to perform writing operations and circuitry from a second of the combinable single-port memory arrays is used to perform reading operations. The availability of the dual-port memory array capability allows users to implement circuits such as first-in-first-out buffers and other circuits that require the ability to perform concurrent read and write operations. When such a dual-port capability is not required, two single-port memory arrays are available to implement a desired logic design.
摘要翻译： 提供了一种可编程逻辑器件存储器阵列电路，其包含一对相关联的可组合单端口存储器阵列。 存储器阵列电路可以具有可变的深度和宽度。 如果需要，可组合的单端口存储器阵列可以独立地操作。 或者，一对可组合单端口存储器阵列可以组合以形成双端口存储器阵列。 当单端口存储器阵列组合以形成双端口存储器阵列时，来自第一可组合单端口存储器阵列的电路用于执行写操作，并且来自第二可组合单端口存储器阵列的电路是 用于执行阅读操作。 双端口存储器阵列功能的可用性允许用户实现诸如先入先出缓冲器和需要执行并发读写操作的其他电路的电路。 当不需要这样的双端口功能时，两个单端口存储器阵列可用于实现期望的逻辑设计。
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公开(公告)号：US06373280B1
公开(公告)日：2002-04-16
申请号：US09795796
申请日：2001-02-28
IPC分类号： A03K19177
CPC分类号： H03K19/17736 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of areas of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such areas. A so-called “fast conductor” network is provided on the device for rapidly and efficiently distributing a relatively small number of signals to substantially any logic area on the device. The fast conductor network has several main conductors that substantially bisect the array in one direction (e.g., by extending parallel to the column axis). Some main conductors can carry signals from off the device. Other main conductors can carry signals generated on the device. The network further includes secondary conductors that extend transverse to the main conductors (e.g., along each row of logic areas). Programmable logic connectors are provided for selectively applying signals from the main conductors to the secondary conductors and from the secondary conductors to the logic areas.
摘要翻译： 可编程逻辑集成电路器件具有多个可编程逻辑区域，该可编程逻辑区域以这种区域的交叉行和列的二维阵列布置在器件上。 在设备上提供了所谓的“快速导体”网络，用于将相对较少数量的信号快速有效地分配到设备上的基本上任何逻辑区域。 快速导体网络具有几个主导体，其在一个方向上基本上平分阵列（例如，通过平行于列轴线延伸）。 一些主导体可以携带离开设备的信号。 其他主导体可以携带在设备上产生的信号。 网络还包括横向于主导体（例如，沿着每一排逻辑区域）延伸的次级导体。 提供可编程逻辑连接器，用于选择性地将信号从主导体施加到次级导体，并从次导体到逻辑区域。
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56.发明授权Programmable logic device memory array circuit having combinable single-port memory arrays 失效具有可组合单端口存储器阵列的可编程逻辑器件存储器阵列电路公开(公告)号：US06288970B1
公开(公告)日：2001-09-11
申请号：US09107926
申请日：1998-06-30
IPC分类号： G11C800
CPC分类号： G11C7/1075 , G11C7/10 , G11C8/16 , G11C11/005
摘要： A programmable logic device memory array circuit is provided that contains a pair of associated combinable single-port memory arrays. The memory array circuit may have a variable depth and width. The combinable single-port memory arrays may be operated independently if desired. Alternatively, a pair of the combinable single-port memory arrays can be combined to form a dual-port memory array. When the single-port memory arrays are combined to form a dual-port memory array, circuitry from a first of the combinable singleport memory arrays is used to perform writing operations and circuitry from a second of the combinable single-port memory arrays is used to perform reading operations. The availability of the dual-port memory array capability allows users to implement circuits such as first-in-first-out buffers and other circuits that require the ability to perform concurrent read and write operations. When such a dual-port capability is not required, two single-port memory arrays are available to implement a desired logic design.
摘要翻译： 提供了一种可编程逻辑器件存储器阵列电路，其包含一对相关联的可组合单端口存储器阵列。 存储器阵列电路可以具有可变的深度和宽度。 如果需要，可组合的单端口存储器阵列可以独立地操作。 或者，一对可组合单端口存储器阵列可以组合以形成双端口存储器阵列。 当单端口存储器阵列组合以形成双端口存储器阵列时，来自第一可组合单端口存储器阵列的电路用于执行写入操作，并且来自第二可组合单端口存储器阵列的电路被用于 执行阅读操作。 双端口存储器阵列功能的可用性允许用户实现诸如先入先出缓冲器和需要执行并发读写操作的其他电路的电路。 当不需要这样的双端口功能时，两个单端口存储器阵列可用于实现期望的逻辑设计。
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57.发明授权Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices 失效减少可编程逻辑器件中硅处理缺陷影响的手段和装置
公开(公告)号：US5592102A
公开(公告)日：1997-01-07
申请号：US545437
申请日：1995-10-19
IPC分类号： G06F11/20 , G06F15/78 , H03K19/177 , H01L25/00
CPC分类号： H03K19/1776 , G06F15/7867 , H03K19/17736 , H03K19/17764
摘要： A programmable logic array integrated circuit has several regular columns of programmable logic circuitry and a spare column which includes a subset of the programmable logic circuitry that is included in a regular column. In the event of a defect in the circuitry in a regular column that is duplicated in the spare column, the regular column logic functions that are thus duplicated are shifted from column to column so that the spare column circuitry is put to use and the defective regular column circuitry is not used. Regular column functions that are not duplicated in the spare column are not shifted. Data for programming the columns is selectively routed to the columns with or without column shifting, depending on whether that data is for functions that are or are not duplicated in the spare column.
摘要翻译： 可编程逻辑阵列集成电路具有几个可编程逻辑电路的常规列和备用列，该备用列包括包含在常规列中的可编程逻辑电路的子集。 在备用列中复制的常规列中的电路中存在缺陷的情况下，由此复制的常规列逻辑功能从列移动到列，使得备用列电路被使用，并且缺陷规则 不使用列电路。 在备用列中未重复的常规列函数不会移动。 用于编程列的数据有选择地路由到具有或不具有列移位的列，这取决于该数据是用于在备用列中是否被复制的功能。
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公开(公告)号：US06225822B1
公开(公告)日：2001-05-01
申请号：US09287048
申请日：1999-04-06
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of areas of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such areas. A so-called “fast conductor” network is provided on the device for rapidly and efficiently distributing a relatively small number of signals to substantially any logic area on the device. The fast conductor network has several main conductors that substantially bisect the array in one direction (e.g., by extending parallel to the column axis). Some main conductors can carry signals from off the device. Other main conductors can carry signals generated on the device. The network further includes secondary conductors that extend transverse to the main conductors (e.g., along each row of logic areas). Programmable logic connectors are provided for selectively applying signals from the main conductors to the secondary conductors and from the secondary conductors to the logic areas.
摘要翻译： 可编程逻辑集成电路器件具有多个可编程逻辑区域，该可编程逻辑区域以这种区域的交叉行和列的二维阵列布置在器件上。 在设备上提供了所谓的“快速导体”网络，用于将相对较少数量的信号快速有效地分配到设备上的基本上任何逻辑区域。 快速导体网络具有几个主导体，其在一个方向上基本上平分阵列（例如，通过平行于列轴线延伸）。 一些主导体可以携带离开设备的信号。 其他主导体可以携带在设备上产生的信号。 网络还包括横向于主导体（例如，沿着每一排逻辑区域）延伸的次级导体。 提供可编程逻辑连接器，用于选择性地将信号从主导体施加到次级导体，并从次导体到逻辑区域。
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公开(公告)号：US06819135B2
公开(公告)日：2004-11-16
申请号：US10047468
申请日：2002-01-14
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of areas of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such areas. A so-called “fast conductor” network is provided on the device for rapidly and efficiently distributing a relatively small number of signals to substantially any logic area on the device. The fast conductor network has several main conductors that substantially bisect the array in one direction (e.g., by extending parallel to the column axis). Some main conductors can carry signals from off the device. Other main conductors can carry signals generated on the device. The network further includes secondary conductors that extend transverse to the main conductors (e.g., along each row of logic areas). Programmable logic connectors are provided for selectively applying signals from the main conductors to the secondary conductors and from the secondary conductors to the logic areas.
摘要翻译： 可编程逻辑集成电路器件具有多个可编程逻辑区域，该可编程逻辑区域以这种区域的交叉行和列的二维阵列布置在器件上。 在设备上提供了所谓的“快速导体”网络，用于将相对较少数量的信号快速有效地分配到设备上的基本上任何逻辑区域。 快速导体网络具有几个主导体，其在一个方向上基本上平分阵列（例如，通过平行于列轴线延伸）。 一些主导体可以携带离开设备的信号。 其他主导体可以携带在设备上产生的信号。 网络还包括横向于主导体（例如，沿着每一排逻辑区域）延伸的次级导体。 提供可编程逻辑连接器，用于选择性地将信号从主导体施加到次级导体，并从次导体到逻辑区域。
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60.发明授权Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices 失效减少可编程逻辑器件中硅处理缺陷影响的手段和装置
公开(公告)号：US5825197A
公开(公告)日：1998-10-20
申请号：US742770
申请日：1996-11-01
IPC分类号： G06F11/20 , G06F15/78 , H03K19/177 , H03K19/003 , H03K19/173
CPC分类号： H03K19/1776 , G06F15/7867 , H03K19/17736 , H03K19/17764
摘要： A programmable logic array integrated circuit has several regular columns of programmable logic circuitry and a spare column which includes a subset of the programmable logic circuitry that is included in a regular column. In the event of a defect in the circuitry in a regular column that is duplicated in the spare column, the regular column logic functions that are thus duplicated are shifted from column to column so that the spare column circuitry is put to use and the defective regular column circuitry is not used. Regular column functions that are not duplicated in the spare column are not shifted. Data for programming the columns is selectively routed to the columns with or without column shifting, depending on whether that data is for functions that are or are not duplicated in the spare column.
摘要翻译： 可编程逻辑阵列集成电路具有几个可编程逻辑电路的常规列和备用列，该备用列包括包含在常规列中的可编程逻辑电路的子集。 在备用列中复制的常规列中的电路中存在缺陷的情况下，由此复制的常规列逻辑功能从列移动到列，使得备用列电路被使用，并且缺陷规则 不使用列电路。 在备用列中未重复的常规列函数不会移动。 用于编程列的数据有选择地路由到具有或不具有列移位的列，这取决于该数据是用于在备用列中是否被复制的功能。
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