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    Programmable logic device with hierarchical interconnection resources
    1.
    发明授权
    Programmable logic device with hierarchical interconnection resources 有权
    具有分层互连资源的可编程逻辑器件

    公开(公告)号：US06417694B1

    公开(公告)日：2002-07-09

    申请号：US09956748

    申请日：2001-09-19

    申请人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

    发明人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

    IPC分类号： H03K19177

    CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

    摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

    摘要翻译： 可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。 水平和垂直超超导区域互连导体分别与每行和列相关联。 每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。 区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。 本地导体与每个区域相关联，主要用于使信号进入该区域。 在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。 可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的 也是当地的导体）。 水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

    Dual port programmable logic device variable depth and width memory array
    8.
    发明授权
    Dual port programmable logic device variable depth and width memory array 有权
    双端口可编程逻辑器件可变深度和宽度存储器阵列

    公开(公告)号：US06392954B2

    公开(公告)日：2002-05-21

    申请号：US09747191

    申请日：2000-12-21

    申请人： Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia ,  Richard G. Cliff ,  Kerry Veenstra

    发明人： Srinivas T. Reddy ,  Christopher F. Lane ,  Manuel Mejia ,  Richard G. Cliff ,  Kerry Veenstra

    IPC分类号： G11C800

    CPC分类号： G11C7/1006

    摘要： A dual-port programmable logic device memory array is provided. Selectable-size data words may be written to and read from the array concurrently. Data is written into the array using write column decoder and data selection logic. The size of the data words handled by the write column decoder and data selection logic is controlled by mode select signals. Data is read from the array using read column decoder and data selection logic. The size of the data words handled by the read column decoder and data selection logic is also controlled by mode select signals. The write column decoder and data selection logic may be used to write data into the memory array at one selected location at the same time that the read column decoder and data selection logic is used to read data from the array at another selected location. A write row address decoder and a read row address decoder are used to independently address individual rows of memory cells in the memory array during writing and reading, respectively.

    摘要翻译： 提供了双端口可编程逻辑器件存储器阵列。 可选择大小的数据字可以并行写入阵列并从阵列中读取。 使用写列解码器和数据选择逻辑将数据写入阵列。 由写列解码器和数据选择逻辑处理的数据字的大小由模式选择信号控制。 使用读列解码器和数据选择逻辑从数组中读取数据。 由读列解码器和数据选择逻辑处理的数据字的大小也由模式选择信号控制。 写列解码器和数据选择逻辑可以用于在一个选定位置将数据写入存储器阵列，同时读列解码器和数据选择逻辑用于在另一选定位置从阵列中读取数据。 写入行地址解码器和读取行地址解码器分别用于在写入和读取期间独立地对存储器阵列中的存储单元的各行进行寻址。