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51.发明申请SOI Semiconductor Device Comprising a Substrate Diode and a Film Diode Formed by Using a Common Well Implantation Mask 有权包括基板二极管的SOI半导体器件和通过使用普通阱植入掩模形成的膜二极管公开(公告)号：US20120181655A1
公开(公告)日：2012-07-19
申请号：US13233762
申请日：2011-09-15
申请人： Thilo Scheiper , Stefan Flachowsky
发明人： Thilo Scheiper , Stefan Flachowsky
IPC分类号： H01L27/12 , H01L21/265
CPC分类号： H01L27/1203 , H01L27/1207
摘要： When forming sophisticated SOI devices, a substrate diode and a film diode are formed by using one and the same implantation mask for determining the well dopant concentration in the corresponding well regions. Consequently, during the further processing, the well dopant concentration of any transistor elements may be achieved independently from the well regions of the diode in the semiconductor layer.
摘要翻译： 当形成复杂的SOI器件时，通过使用一个相同的注入掩模来形成衬底二极管和膜二极管，以确定相应阱区中的阱掺杂剂浓度。 因此，在进一步处理期间，可以独立于半导体层中的二极管的阱区实现任何晶体管元件的阱掺杂剂浓度。
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52.发明申请Patterning of a Stressed Dielectric Material in a Contact Level Without Using an Underlying Etch Stop Layer 审中-公开在不使用底层蚀刻停止层的情况下，接触层中的压电介电材料的图案化公开(公告)号：US20120156839A1
公开(公告)日：2012-06-21
申请号：US13191870
申请日：2011-07-27
申请人： Thilo Scheiper , Sven Beyer , Jan Hoentschel , Stefan Flachowsky
发明人： Thilo Scheiper , Sven Beyer , Jan Hoentschel , Stefan Flachowsky
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823878
摘要： An efficient strain-inducing mechanism may be implemented in the form of differently stressed material layers that are formed above transistors of different types. The strain-inducing dielectric materials may be formed so as to be in direct contact with the corresponding transistors, thereby enhancing the overall strain transfer efficiency. Moreover, the disclosed manufacturing strategy avoids or at least significantly reduces any interaction of reactive etch atmospheres used to pattern the strain-inducing material layers with metal silicide regions, which may be formed individually for each type of transistor.
摘要翻译： 可以以不同类型的晶体管上形成的不同应力材料层的形式实施有效的应变诱导机构。 应变诱导电介质材料可以形成为与相应的晶体管直接接触，从而提高总的应变转移效率。 此外，所公开的制造策略避免或至少显着减少用于将应变诱导材料层图案化为金属硅化物区域的反应性蚀刻气氛的任何相互作用，金属硅化物区域可以针对每种类型的晶体管单独形成。
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53.发明申请Strain Engineering in Three-Dimensional Transistors Based on a Strained Channel Semiconductor Material 审中-公开基于应变通道半导体材料的三维晶体管中的应变工程公开(公告)号：US20120025312A1
公开(公告)日：2012-02-02
申请号：US13164928
申请日：2011-06-21
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L21/823821 , H01L21/823807 , H01L29/66795 , H01L29/7843 , H01L29/7848 , H01L29/785
摘要： In three-dimensional transistor configurations, such as finFETs, at least one surface of the semiconductor fin may be provided with a strained semiconductor material, which may thus have a pronounced uniaxial strain component along the current flow direction. The strained semiconductor material may be provided at any appropriate manufacturing stage, for instance, prior to actually patterning the semiconductor fins and/or after the patterning the semiconductor fins, thereby providing superior performance and flexibility in adjusting the overall characteristics of three-dimensional transistors.
摘要翻译： 在诸如finFET的三维晶体管配置中，半导体鳍片的至少一个表面可以设置有应变半导体材料，其可以沿着当前流动方向具有明显的单轴应变分量。 应变半导体材料可以在任何适当的制造阶段提供，例如，在实际构图半导体鳍片之前和/或在图案化半导体鳍片之后，从而在调整三维晶体管的整体特性方面提供优异的性能和灵活性。
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54.发明授权Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations 有权在28nm低功率/高性能技术上使用硅氧化物封装，早期晕圈和延伸注入的PMOS器件的晚期原位掺杂SiGe结公开(公告)号：US08936977B2
公开(公告)日：2015-01-20
申请号：US13482393
申请日：2012-05-29
IPC分类号： H01L21/338
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L29/0847 , H01L29/1054 , H01L29/458 , H01L29/4925 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.
摘要翻译： 提供具有PMOS eSiGe源极/漏极区域的HKMG器件。 实施例包括在衬底上形成第一和第二HKMG栅极堆叠，在每个HKMG栅极堆叠的每一侧上形成氮化物衬垫和氧化物衬垫，在每个HKMG栅极堆叠的每一侧执行卤素/延伸注入，形成氧化物衬垫和氮化物衬垫 在每个HKMG栅极堆叠的氧化物间隔物上，在第二HKMG栅极堆叠的相对侧形成深的源极/漏极区域，在第二HKMG栅极堆叠层上形成氧化物硬掩模，在第一金属间化合物栅极堆叠的相对侧形成嵌入的硅锗（eSiGe） HKMG栅极堆叠，并去除氧化物硬掩模。
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公开(公告)号：US08679921B2
公开(公告)日：2014-03-25
申请号：US13283370
申请日：2011-10-27
申请人： Stefan Flachowsky , Thilo Scheiper
发明人： Stefan Flachowsky , Thilo Scheiper
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L29/0653 , H01L29/0692 , H01L29/41758 , H01L29/41766 , H01L29/41775 , H01L29/4238 , H01L29/456 , H01L29/66666 , H01L29/78 , H01L29/7848
摘要： Lithographic limitations on gate and induced channel length in MOSFETS are avoided by forming non-planar MOSFETS in a cavity extending into a semiconductor substrate. The gate insulator and channel region lie proximate a cavity sidewall having angle α preferably about ≧90 degrees with respect to the semiconductor surface. The channel length depends on the bottom depth of the cavity and the depth from the surface of a source or drain region adjacent the cavity. The corresponding drain or source lies at the cavity bottom. The cavity sidewall extends therebetween. Neither depth is lithographic dependent. Very short channels can be consistently formed, providing improved performance and manufacturing yield. Source, drain and gate connections are brought to the same surface so that complex circuits can be readily constructed. The source and drain regions are preferably formed epitaxially and strain inducing materials can be used therein to improve channel carrier mobility.
摘要翻译： 通过在延伸到半导体衬底的腔中形成非平面MOSFET，可以避免MOSFETS中栅极和感应沟道长度的光刻限制。 栅极绝缘体和沟道区域靠近具有相对于半导体表面的角度α优选地约≥90度的空腔侧壁。 通道长度取决于空腔的底部深度以及与空腔相邻的源极或漏极区域的表面的深度。 相应的漏极或源极位于腔底。 空腔侧壁在其间延伸。 两个深度都不是光刻依赖的。 可以一贯形成非常短的通道，从而提高性能和制造成品率。 源极，漏极和栅极连接被带到相同的表面，使得可以容易地构造复杂的电路。 源区和漏区优选地外延形成，并且应变诱导材料可用于其中以改善沟道载流子迁移率。
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56.发明授权Low-diffusion drain and source regions in CMOS transistors for low power/high performance applications 有权用于低功耗/高性能应用的CMOS晶体管中的低扩散漏极和源极区域公开(公告)号：US08664068B2
公开(公告)日：2014-03-04
申请号：US13192620
申请日：2011-07-28
IPC分类号： H01L21/336 , H01L21/36
CPC分类号： H01L21/823807 , H01L21/823814
摘要： The drain and source regions may at least be partially formed by in situ doped epitaxially grown semiconductor materials for complementary transistors in sophisticated semiconductor devices designed for low power and high performance applications. To this end, cavities may be refilled with in situ doped semiconductor material, which in some illustrative embodiments also provides a desired strain in the channel regions of the complementary transistors.
摘要翻译： 漏极和源极区域可以至少部分地由原位掺杂的外延生长的半导体材料形成，用于为低功率和高性能应用设计的复杂半导体器件中的互补晶体管。 为此，空穴可以用原位掺杂的半导体材料重新填充，在一些说明性实施例中，还可以在互补晶体管的沟道区域中提供期望的应变。
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57.发明授权Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts 有权具有基板触点的集成电路的制造方法和具有基板触点的集成电路公开(公告)号：US08609533B2
公开(公告)日：2013-12-17
申请号：US13436323
申请日：2012-03-30
IPC分类号： H01L21/311 , H01L21/314 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/76816 , H01L21/28518 , H01L21/743 , H01L21/76802 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts are provided. One method includes forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate. A metal silicide region is formed in the silicon substrate exposed by the first trench. A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. An ILD layer of dielectric material is formed overlying the second stress-inducing layer. A second trench is formed extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region. The second trench is filled with a conductive material.
摘要翻译： 提供了具有基板触点的集成电路的制造方法和具有基板触点的集成电路。 一种方法包括在穿过掩埋绝缘层延伸到硅衬底的SOI衬底中形成第一沟槽。 在由第一沟槽暴露的硅衬底中形成金属硅化物区域。 第一应力诱导层形成在金属硅化物区域之上。 第二应力诱导层形成在第一应力诱导层上。 介电材料的ILD层形成在第二应力诱导层上。 形成延伸穿过ILD层和第一和第二应力诱导层到金属硅化物区域的第二沟槽。 第二沟槽填充有导电材料。
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58.发明申请METHODS OF PERFORMING HIGHLY TILTED HALO IMPLANTATION PROCESSES ON SEMICONDUCTOR DEVICES 有权在半导体器件上执行高度倾斜的HALO植入工艺的方法公开(公告)号：US20130323892A1
公开(公告)日：2013-12-05
申请号：US13487351
申请日：2012-06-04
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823412 , H01L21/26586 , H01L21/823807 , H01L29/1083 , H01L29/66628 , H01L29/66636
摘要： One illustrative method disclosed herein involves forming first and second gate structures that include a cap layer for a first transistor device and a second transistor device, respectively, wherein the first and second transistors are oriented transverse to one another, performing a first halo ion implant process to form first halo implant regions for the first transistor with the cap layer in position in the first gate structure of the first transistor, removing the cap layer from at least the second gate structure of the second transistor and, after removing the cap layer, performing a second halo ion implant process to form second halo implant regions for the second transistor, wherein the first and second halo implant processes are performed at transverse angles relative to the substrate.
摘要翻译： 本文公开的一种说明性方法包括分别形成包括用于第一晶体管器件和第二晶体管器件的帽层的第一和第二栅极结构，其中第一和第二晶体管彼此横向取向，执行第一晕圈离子注入工艺 以形成第一晶体管的第一晕环注入区，其中盖层位于第一晶体管的第一栅极结构中的位置，从至少第二晶体管的第二栅极结构去除覆盖层，并且在去除覆盖层之后，执行 第二晕圈离子注入工艺以形成用于第二晶体管的第二晕环注入区，其中第一和第二晕环注入工艺以相对于衬底的横向角度进行。
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59.发明授权Methods of performing highly tilted halo implantation processes on semiconductor devices 有权在半导体器件上执行高度倾斜的晕圈注入工艺的方法公开(公告)号：US08598007B1
公开(公告)日：2013-12-03
申请号：US13487351
申请日：2012-06-04
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/26586 , H01L21/823807 , H01L29/1083 , H01L29/66628 , H01L29/66636
摘要： One illustrative method disclosed herein involves forming first and second gate structures that include a cap layer for a first transistor device and a second transistor device, respectively, wherein the first and second transistors are oriented transverse to one another, performing a first halo ion implant process to form first halo implant regions for the first transistor with the cap layer in position in the first gate structure of the first transistor, removing the cap layer from at least the second gate structure of the second transistor and, after removing the cap layer, performing a second halo ion implant process to form second halo implant regions for the second transistor, wherein the first and second halo implant processes are performed at transverse angles relative to the substrate.
摘要翻译： 本文公开的一种说明性方法包括分别形成包括用于第一晶体管器件和第二晶体管器件的帽层的第一和第二栅极结构，其中第一和第二晶体管彼此横向取向，执行第一晕圈离子注入工艺 以形成第一晶体管的第一晕环注入区，其中盖层位于第一晶体管的第一栅极结构中的位置，从至少第二晶体管的第二栅极结构去除覆盖层，并且在去除覆盖层之后，执行 第二晕圈离子注入工艺以形成用于第二晶体管的第二晕环注入区，其中第一和第二晕环注入工艺以相对于衬底的横向角度进行。
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公开(公告)号：US20130313572A1
公开(公告)日：2013-11-28
申请号：US13953349
申请日：2013-07-29
CPC分类号： H01L29/78 , H01L21/26586 , H01L29/1608 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/7848
摘要： Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions.
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