公开(公告)号：US5965218A

公开(公告)日：1999-10-12

申请号：US819283

申请日：1997-03-18

Applicant: Subhas Bothra ,  Ling Q. Qian

Inventor： Subhas Bothra ,  Ling Q. Qian

IPC: G01Q70/06 ,  G01Q60/16 ,  G01Q60/38 ,  G01Q70/14 ,  G01Q70/16 ,  B05D5/12 ,  H01J9/04 ,  H05H1/24

CPC classification number: G01Q60/16 ,  B82Y35/00 ,  G01Q60/38 ,  H01J2209/022

Abstract: A method for manufacturing probe tips suitable for use in an atomic force microscope (AFM) or scanning tunneling microscope (STM) begins by depositing a layer of a first material over a substrate and then patterning the layer of the first material to define apertures wherever probe tips are to be formed. Next, a layer of a second material is deposited using an unbiased high density plasma chemical vapor deposition (HDPCVD) process to form sharp probe tips in the apertures in the layer of the first material. The HDPCVD process also forms a sacrificial layer of the second material on top of the portions of the first material not removed by the patterning step. The sacrificial layer at least partially overhangs the apertures in the first material, forming a shadow mask during the deposition process which gives rise to a sharp probe profile. After the formation of the probe tips, the remaining portion of the layer of first material is removed using a wet chemical etchant that selectively etches the first material at a much higher rate than the second material. The removing step also removes the sacrificial layer of the second material because the sacrificial layer is lifted off the substrate when the underlying layer of first material is etched away. In one preferred embodiment, the first material is silicon nitride and the second material is silicon dioxide.

Abstract translation: 用于制造适于在原子力显微镜（AFM）或扫描隧道显微镜（STM）中使用的探针尖端的方法开始于在衬底上沉积第一材料层，然后对第一材料的层进行图案以在探针 要形成技巧。 接下来，使用无偏高密度等离子体化学气相沉积（HDPCVD）工艺沉积第二材料层，以在第一材料层中的孔中形成尖锐的探针尖端。 HDPCVD工艺还在未被图案化步骤去除的第一材料的部分的顶部上形成第二材料的牺牲层。 牺牲层至少部分地悬挂在第一材料中的孔中，在沉积过程期间形成荫罩，其产生尖锐的探针轮廓。 在形成探针尖端之后，使用湿化学蚀刻剂去除第一材料层的剩余部分，其以比第二材料高得多的速率选择性地蚀刻第一材料。 当第一材料的下层被蚀刻掉时，去除步骤也会去除第二材料的牺牲层，因为牺牲层被从衬底上提起。 在一个优选实施例中，第一材料是氮化硅，第二材料是二氧化硅。

公开(公告)号：US5963784A

公开(公告)日：1999-10-05

申请号：US853853

申请日：1997-05-09

Applicant: Subhas Bothra ,  Xi-Wei Lin

Inventor： Subhas Bothra ,  Xi-Wei Lin

IPC: H01L21/66 ,  H01L23/544 ,  G01R31/26 ,  G01R27/08

CPC classification number: H01L22/34 ,  H01L22/12

Abstract: The present invention provides methods of determining a smallest dimension of a fabricated device on a semiconductor substrate, methods of determining width of a structure comprising a refractory metal silicide, methods of determining parameters of a semiconductor device comprising a refractory metal silicide, and methods of determining width of an insulative spacer of a semiconductor device. One aspect of the present invention provides a method of determining a smallest dimension of a fabricated device on a semiconductor substrate comprising: providing a first substrate area and a second substrate area; subjecting the first substrate area and the second substrate area to the same processing conditions to achieve regions of like material on the first and second substrate areas, the like material in the first area having a smallest dimension which is greater than a smallest dimension of the like material in the second area; determining parameters of the first substrate area; and determining said smallest dimension of the like material in the second substrate area using the determined parameters of the first substrate area.

Abstract translation: 本发明提供了确定半导体衬底上制造的器件的最小尺寸的方法，确定包括难熔金属硅化物的结构的宽度的方法，确定包括难熔金属硅化物的半导体器件的参数的方法，以及确定方法 半导体器件的绝缘间隔物的宽度。 本发明的一个方面提供一种确定半导体衬底上的制造器件的最小尺寸的方法，包括：提供第一衬底区域和第二衬底区域; 对第一基板区域和第二基板区域进行相同的处理条件以在第一和第二基板区域上实现类似材料的区域，第一区域中的类似材料具有大于等于最小尺寸的最小尺寸 第二区的材料; 确定第一衬底区域的参数; 以及使用所确定的所述第一衬底区域的参数来确定所述第二衬底区域中的所述相似材料的所述最小尺寸。

公开(公告)号：US5916016A

公开(公告)日：1999-06-29

申请号：US956836

申请日：1997-10-23

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: B24B37/10 ,  B24B37/30 ,  B24B49/16 ,  B24B5/00

CPC classification number: B24B37/107 ,  B24B37/30 ,  B24B49/16

Abstract: Disclosed is a chemical mechanical polishing system. The system includes a mechanical arm and a carrier body that is configured to be coupled to the mechanical arm. The carrier body has a recessed portion for retaining a semiconductor wafer. The recessed portion has a carrier film that is in direct contact with a back side of the semiconductor wafer. The system further includes a plurality of pressure rings that are defined in the carrier body, such that the plurality of pressure rings are in direct contact with the carrier film. Each of the plurality of pressure rings are used to apply a selected pressure to the carrier film, such that the carrier film produces a back pressure against the back side of the semiconductor wafer. The back pressure is configured to be consistent with the selected pressure that is applied to each of the plurality of pressure rings. Whereby the selected pressure that is applied to each of the plurality of pressure rings controls a polishing rate in a plurality of concentric areas of the semiconductor wafer that correspond to the plurality of pressure rings.

Abstract translation: 公开了一种化学机械抛光系统。 该系统包括机械臂和被配置为联接到机械臂的承载体。 载体主体具有用于保持半导体晶片的凹部。 凹部具有与半导体晶片的背面直接接触的载体膜。 系统还包括限定在载体主体中的多个压力环，使得多个压力环与载体膜直接接触。 多个压力环中的每一个用于将所选择的压力施加到载体膜，使得载体膜产生抵抗半导体晶片背面的背压。 背压构造成与施加到多个压力环中的每一个的所选择的压力一致。 由此施加到多个压力环中的每一个的所选择的压力控制对应于多个压力环的半导体晶片的多个同心区域中的抛光速率。

公开(公告)号：US5540958A

公开(公告)日：1996-07-30

申请号：US357842

申请日：1994-12-14

Applicant: Subhas Bothra ,  Milind G. Weling

Inventor： Subhas Bothra ,  Milind G. Weling

IPC: G01N37/00 ,  G01Q60/38 ,  G01Q70/14 ,  G01Q70/16 ,  G02B21/32 ,  H05H1/00

CPC classification number: G01Q60/38 ,  B82Y35/00 ,  G01Q70/06

Abstract: A method of manufacturing a microscope probe tip comprises the steps of depositing a first material over a substrate, such as silicon oxide over a silicon substrate using chemical vapor deposition. The first material is patterned to define at least one structural protrusion. During this patterning, the first material is etched back. Then a second material, such as silicon oxide, is deposited over the protrusion using an electron cyclotron resonance (ECR) process, which grows a sloped surface to form the microscope probe tip. In another aspect of the invention, two different resolution Atomic Force Microscope (AFM) probe tips are grown. Then, the cantilevers are coupled together to provide an AFM with two probe tips having different resolutions.

Abstract translation: 制造显微镜探针尖端的方法包括以下步骤：使用化学气相沉积在硅衬底上在诸如氧化硅的衬底上沉积第一材料。 图案化第一材料以限定至少一个结构突起。 在该图案化期间，第一材料被回蚀。 然后使用电子回旋共振（ECR）工艺在突起上沉积第二种材料，例如氧化硅，其生长倾斜表面以形成显微镜探针尖端。 在本发明的另一方面，生长了两种不同分辨率的原子力显微镜（AFM）探针尖端。 然后，悬臂连接在一起，为AFM提供具有不同分辨率的两个探针头。

公开(公告)号：US07489221B2

公开(公告)日：2009-02-10

申请号：US11504073

申请日：2006-08-15

Applicant: Carol Barrett ,  Tom McKay ,  Subhas Bothra

Inventor： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC: H01F5/00

CPC classification number: H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

Abstract translation: 公开了一种电感器电路。 电感器电路包括第一硅芯片电感器和第二硅芯片电感器，每个具有多个匝数。 第二硅电感器的多圈的一部分形成在第一硅内感应器的匝之间。 第一和第二硅内电感器被配置为使得流过第一硅芯片电感器和第二硅芯片电感器的差分电流在相应的电感圈中以相同的方向流动。

公开(公告)号：US06411367B1

公开(公告)日：2002-06-25

申请号：US09280174

申请日：1999-03-29

Applicant: Daniel C. Baker ,  Subhas Bothra ,  Satyendra Sethi

Inventor： Daniel C. Baker ,  Subhas Bothra ,  Satyendra Sethi

IPC: G03B2754

CPC classification number: G03F7/70108 ,  G02B27/58 ,  G03F7/70225

Abstract: A system and method is disclosed for enhancing an optical lithography process by capturing light diffracted from a mask having features to be exposed onto a wafer. In one embodiment, a system of the present invention has in place a mask, a wafer and a reduction lens such that the reduction lens is placed between the mask and the wafer in order to direct and expose the mask's features onto the wafer. Furthermore, a reflective member is disposed proximate to the reduction lens. In order to achieve finer resolution of the mask image on the wafer, this reflective member captures diffracted light diffracting beyond the reduction lens and redirects the diffracted light to pass through the reduction lens such that the diffracted light is redirected onto the wafer. In so doing, the reflective member resolves the mask image on the wafer in more detail than is possible by an optical lithography process using no such reflective member.

Abstract translation: 公开了一种用于通过捕获从具有要暴露于晶片上的特征的掩模衍射的光来增强光刻工艺的系统和方法。 在一个实施例中，本发明的系统具有掩模，晶片和还原透镜，使得将还原透镜放置在掩模和晶片之间，以便将掩模的特征引导并暴露在晶片上。 此外，反射构件设置在靠近减速透镜的位置。 为了获得晶片上的掩模图像的更精细的分辨率，该反射构件捕获衍射光超出了还原透镜的衍射光，并且重定向衍射光以通过还原透镜，使得衍射光被重定向到晶片上。 在这样做时，反射构件比不使用这种反射构件的光学光刻工艺更可靠地解决晶片上的掩模图像。

公开(公告)号：US06399432B1

公开(公告)日：2002-06-04

申请号：US09199203

申请日：1998-11-24

Applicant: Tammy Zheng ,  Subhas Bothra

Inventor： Tammy Zheng ,  Subhas Bothra

IPC: H01L218238

CPC classification number: H01L21/823842 ,  H01L21/28035

Abstract: For use with sub-micron CMOS technologies, a gate etch process improves control of the etch profile. Gate stacks utilize N-type or P-type doped amorphous or poly silicon to enhance device performance. However, the different etching characteristics of the N-type versus the P-type amorphous or poly silicon material can result in a localized breakthrough of the underlying thin gate oxide adjacent to the edge of the gate stack, especially in the N doped active regions. According to one example embodiment, this localized breakthrough (“microtrenching”) is avoided by building the gate stacks with undoped amorphous or poly silicon to the desired configuration, masking the gate stacks with a dielectric layer, planarizing the dielectric layer and then implanting the N-type or P-type species into the selected gate stack.

Abstract translation: 为了与亚微米CMOS技术一起使用，栅极蚀刻工艺改善了蚀刻轮廓的控制。 栅堆叠利用N型或P型掺杂的非晶或多晶硅来提高器件性能。 然而，N型相对于P型非晶或多晶硅材料的不同蚀刻特性可导致邻近栅极叠层边缘的底层薄栅极氧化物的局部穿透，特别是在N掺杂有源区中。 根据一个示例实施例，通过将具有未掺杂的非晶或多晶硅的栅极堆叠构建成所需的配置来避免该局部突破（“微切割”），用介电层掩蔽栅极堆叠，平坦化介电层，然后将N 型或P型物质进入选定的栅极堆叠。

公开(公告)号：US06372522B1

公开(公告)日：2002-04-16

申请号：US09631059

申请日：2000-08-01

Applicant: Milind Ganesh Weling ,  Subhas Bothra ,  Satyendra Sethi

Inventor： Milind Ganesh Weling ,  Subhas Bothra ,  Satyendra Sethi

IPC: H01L2100

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system for repairable interconnect links using laser energy in a semiconductor integrated circuit die. The integrated circuit die is fabricated to include a plurality of interconnect links. At least a first and a second interconnect element are included in the integrated circuit die. The first and second interconnect elements are couple via an interconnect link. An anti-reflective layer is disposed on a surface above the interconnect link. The anti-reflective layer is configured to increase an amount of laser energy absorbed by the interconnect link in order to fuse the interconnect link, and thereby repair the integrated circuit die.

Abstract translation: 一种用于在半导体集成电路管芯中使用激光能量的可修复互连链路的系统。 集成电路管芯被制造成包括多个互连连接。 至少第一和第二互连元件包括在集成电路管芯中。 第一和第二互连元件经由互连链路耦合。 抗反射层设置在互连连接件上的表面上。 防反射层被配置为增加由互连链路吸收的激光能量的量，以便熔断互连链路，从而修复集成电路管芯。

公开(公告)号：US06355969B1

公开(公告)日：2002-03-12

申请号：US09405043

申请日：1999-09-27

Applicant: Stephen L. Skala ,  Subhas Bothra

Inventor： Stephen L. Skala ,  Subhas Bothra

IPC: H01L2144

CPC classification number: H01L23/5256 ,  H01L21/76879 ,  H01L21/76892 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for making, and a programmable structure for use in a semiconductor chip is provided. The method includes forming a lower metallization layer, and forming an upper metallization layer. The upper metallization layer has a first portion and a second portion. An eroded via is formed between the lower metallization layer and the first portion of the upper metallization layer, and a conductive via is formed between the lower metallization layer and the second portion of the upper metallization layer. The method then includes applying a current between the lower metallization layer and the second portion of the upper metallization layer. The current is configured to cause electromigration in the lower metallization layer such that some of the electromigration fills the eroded via between the lower metallization layer and first portion of the upper metallization layer. The current, if programming is desired, is applied from pads of the semiconductor chip either directly or by way of a programming circuit.

Abstract translation: 提供了制造方法和用于半导体芯片的可编程结构。 该方法包括形成下金属化层，并形成上金属化层。 上金属化层具有第一部分和第二部分。 在下金属化层和上金属化层的第一部分之间形成侵蚀通孔，并且在下金属化层和上金属化层的第二部分之间形成导电通孔。 该方法然后包括在下部金属化层和上部金属化层的第二部分之间施加电流。 电流被配置为在下金属化层中引起电迁移，使得一些电迁移填充下金属化层和上金属化层的第一部分之间的侵蚀通孔。 如果需要编程，则电流直接地或通过编程电路施加于半导体芯片的焊盘。

公开(公告)号：US06327695B1

公开(公告)日：2001-12-04

申请号：US09451668

申请日：1999-11-30

Applicant: Subhas Bothra ,  Paul R. Findley

Inventor： Subhas Bothra ,  Paul R. Findley

IPC: G06F1750

CPC classification number: H01L21/76224 ,  H01L21/763

Abstract: Disclosed is a network of on-chip capacitive structures for suppressing power supply inductive noise, methods for making, and systems for designing the on-chip capacitive structures. The network includes a plurality of dummy active regions that are dispersed throughout an integrated circuit design that has a plurality of active regions. The plurality of dummy active regions are separated from the plurality of active regions by at least a bloat distance. The network further includes a network of dummy polysilicon lines that are configured to overlie selected dummy active regions. The network of dummy polysilicon lines that overlie the selected dummy active regions function as dummy gates. In this embodiment, the selected dummy active regions and the dummy polysilicon lines that overlie the selected dummy active regions form the network of on-chip capacitive structures.

Abstract translation: 公开了用于抑制电源感应噪声的片上电容结构网络，制造方法以及用于设计片上电容结构的系统。 网络包括分散在具有多个有源区域的集成电路设计中的多个虚拟有源区域。 多个虚拟有源区域与多个有源区域分开至少一个膨胀距离。 该网络还包括虚拟多晶硅线路网络，其被配置为覆盖所选择的虚拟有源区域。 覆盖所选择的虚拟有源区域的虚拟多晶硅线的网络用作虚拟栅极。 在本实施例中，所选择的虚拟有源区和覆盖所选择的虚拟有源区的虚拟多晶硅线形成片上电容结构的网络。