公开(公告)号：US5882998A

公开(公告)日：1999-03-16

申请号：US55018

申请日：1998-04-03

Applicant: Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

Inventor： Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

IPC: H01C13/00 ,  H01L21/822 ,  H01L23/525 ,  H01L27/04 ,  H01L29/00

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.

Abstract translation: 公开了具有低功率编程阈值和抗逆向工程特性的半导体熔丝结构。 熔丝结构包括具有场氧化物区域的衬底。 具有增加的掺杂剂浓度区域的多晶硅条带位于场氧化物区域之上。 熔丝结构还包括具有位于多晶硅条上的第一和第二区域的硅化金属化层。 第一区域具有第一厚度，并且第二区域具有小于第一厚度的第二厚度，并且基本上位于多晶硅条的增加的掺杂剂浓度区域之上。 优选地，硅化金属化层的第一区域具有位于第二区域的相对侧上的第一侧和第二侧，并且所得到的熔丝结构的形状基本上是矩形。 因此，可以通过断开第二区域来编程半导体熔丝结构。

公开(公告)号：US5963784A

公开(公告)日：1999-10-05

申请号：US853853

申请日：1997-05-09

Applicant: Subhas Bothra ,  Xi-Wei Lin

Inventor： Subhas Bothra ,  Xi-Wei Lin

IPC: H01L21/66 ,  H01L23/544 ,  G01R31/26 ,  G01R27/08

CPC classification number: H01L22/34 ,  H01L22/12

Abstract: The present invention provides methods of determining a smallest dimension of a fabricated device on a semiconductor substrate, methods of determining width of a structure comprising a refractory metal silicide, methods of determining parameters of a semiconductor device comprising a refractory metal silicide, and methods of determining width of an insulative spacer of a semiconductor device. One aspect of the present invention provides a method of determining a smallest dimension of a fabricated device on a semiconductor substrate comprising: providing a first substrate area and a second substrate area; subjecting the first substrate area and the second substrate area to the same processing conditions to achieve regions of like material on the first and second substrate areas, the like material in the first area having a smallest dimension which is greater than a smallest dimension of the like material in the second area; determining parameters of the first substrate area; and determining said smallest dimension of the like material in the second substrate area using the determined parameters of the first substrate area.

Abstract translation: 本发明提供了确定半导体衬底上制造的器件的最小尺寸的方法，确定包括难熔金属硅化物的结构的宽度的方法，确定包括难熔金属硅化物的半导体器件的参数的方法，以及确定方法 半导体器件的绝缘间隔物的宽度。 本发明的一个方面提供一种确定半导体衬底上的制造器件的最小尺寸的方法，包括：提供第一衬底区域和第二衬底区域; 对第一基板区域和第二基板区域进行相同的处理条件以在第一和第二基板区域上实现类似材料的区域，第一区域中的类似材料具有大于等于最小尺寸的最小尺寸 第二区的材料; 确定第一衬底区域的参数; 以及使用所确定的所述第一衬底区域的参数来确定所述第二衬底区域中的所述相似材料的所述最小尺寸。

公开(公告)号：US5985749A

公开(公告)日：1999-11-16

申请号：US881614

申请日：1997-06-25

Applicant: Xi-Wei Lin ,  Subhas Bothra

Inventor： Xi-Wei Lin ,  Subhas Bothra

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L21/76843

Abstract: The invention relates to integrated circuits and to via hole structures which include a tungsten silicide barrier layer and to methods of forming such via hole structures. In an exemplary embodiment, a metal layer is formed on a sidewall and a bottom surface of the via hole, a WSi.sub.x barrier layer is formed on the first metal layer by chemical vapor deposition and the via hole is subsequently filled with a metal. The tungsten silicide barrier layer effectively suppresses device degradation resulting from the release of gaseous species from the sidewall of the via hole during plug formation. Semiconductor devices can thus be fabricated which are immune or less susceptible to metal open failures due to incomplete via filling.

Abstract translation: 本发明涉及集成电路和包括硅化钨阻挡层的通孔结构以及形成这种通孔结构的方法。 在一个示例性实施例中，在通孔的侧壁和底表面上形成金属层，通过化学气相沉积在第一金属层上形成WSix阻挡层，随后填充金属孔。 硅化钨阻挡层有效地抑制了在插塞形成期间从气孔物质从通孔的侧壁释放出来的装置劣化。 因此可以制造半导体器件，其由于不完全的通孔填充而免疫或不易受金属开路故障的影响。

公开(公告)号：US5854510A

公开(公告)日：1998-12-29

申请号：US883403

申请日：1997-06-26

Applicant: Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

Inventor： Harlan Lee Sur, Jr. ,  Subhas Bothra ,  Xi-Wei Lin ,  Martin H. Manley ,  Robert Payne

IPC: H01C13/00 ,  H01L21/822 ,  H01L23/525 ,  H01L27/04 ,  H01L27/10 ,  H01L29/00

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.

Abstract translation: 公开了具有低功率编程阈值和抗逆向工程特性的半导体熔丝结构。 熔丝结构包括具有场氧化物区域的衬底。 具有增加的掺杂剂浓度区域的多晶硅条带位于场氧化物区域之上。 熔丝结构还包括具有位于多晶硅条上的第一和第二区域的硅化金属化层。 第一区域具有第一厚度，并且第二区域具有小于第一厚度的第二厚度，并且基本上位于多晶硅条的增加的掺杂剂浓度区域之上。 优选地，硅化金属化层的第一区域具有位于第二区域的相对侧上的第一侧和第二侧，并且所得到的熔丝结构的形状基本上是矩形。 因此，可以通过断开第二区域来编程半导体熔丝结构。

公开(公告)号：US5834356A

公开(公告)日：1998-11-10

申请号：US883814

申请日：1997-06-27

Applicant: Subhas Bothra ,  Dipankar Pramanik ,  Xi-Wei Lin

Inventor： Subhas Bothra ,  Dipankar Pramanik ,  Xi-Wei Lin

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/20

CPC classification number: H01L28/24 ,  H01L21/28518 ,  H01L28/20

Abstract: Disclosed is a method for making a high resistive structure in a salicided process. The method includes providing a substrate including at least one active device having diffusion regions and a polysilicon gate structure. Depositing a metallization layer over the substrate including at least one active device. Annealing the substrate to cause at least part of metallization layer to form a metallization silicided layer over the substrate that includes the at least one active device. Preferably, the metallization silicided layer lying over the diffusion regions and the polysilicon gate produces a substantially decreased level of sheet resistance. The method also includes forming a mask over the metallization silicided layer, and the mask being configured to leave a portion of the metallization silicided layer that overlies at least one active device exposed. Further, the method includes etching the substrate in order to remove the exposed metallization silicided layer overlying the at least one active device to produce a substantially increased level of sheet resistance over the at least one active device not having the metallization silicided layer.

Abstract translation: 本发明公开了一种在水银工艺中制作高电阻结构的方法。 该方法包括提供包括至少一个具有扩散区的有源器件和多晶硅栅极结构的衬底。 在包括至少一个有源器件的衬底上沉积金属化层。 退火衬底以使至少部分金属化层在包括至少一个有源器件的衬底上形成金属化硅化物层。 优选地，位于扩散区域和多晶硅栅极上方的金属化硅化物层产生显着降低的薄层电阻水平。 该方法还包括在金属化硅化物层上形成掩模，并且掩模被配置为留下覆盖至少一个暴露的有源器件的金属化硅化物层的一部分。 此外，该方法包括蚀刻衬底以去除覆盖至少一个有源器件的暴露的金属化硅化物层，以在不具有金属化硅化物层的至少一个有源器件上产生基本上增加的片电阻水平。

公开(公告)号：US20110163831A1

公开(公告)日：2011-07-07

申请号：US13047699

申请日：2011-03-14

Applicant: Carol Barrett ,  Tom McKay ,  Subhas Bothra

Inventor： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC: H01F5/00

CPC classification number: H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

Abstract translation: 公开了一种电感器电路。 电感器电路包括第一硅芯片电感器和第二硅芯片电感器，每个具有多个匝数。 第二硅电感器的多圈的一部分形成在第一硅内感应器的匝之间。 第一和第二硅内电感器被配置为使得流过第一硅芯片电感器和第二硅芯片电感器的差分电流在相应的电感圈中以相同的方向流动。

公开(公告)号：US07614024B2

公开(公告)日：2009-11-03

申请号：US11244514

申请日：2005-10-06

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

Abstract: Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known solutions where metal fill was performed after design and layout, performing metal fill during layout with a uniform pattern of conductive traces sized and spaced according to the design rules of the device to be fabricated resulting in more planning and design. Dividing the conductive traces into active and inactive segments during the design and layout identifies potentially negative impacts on critical or sensitive device elements within the device during design and layout. Previously, metal fill was implemented after design and layout and often resulted in negative impacts not previously accounted for during IC design. Embodiments of the present invention reduce degradation, seen in other devices where metal fill is incorporated after design and layout. Additionally, because the physical characteristics of inactive metal fill segments are considered during design and layout of the ICs.

Abstract translation: 本发明的实施例提供了一种系统和方法，用于在设计期间使用诸如位置和路线工具或布局工具的工具来实现金属填充。 与在设计和布局之后执行金属填充的现有已知解决方案不同，在布局期间，根据要制造的器件的设计规则，均匀地形成导电迹线图案并进行间隔，从而实现更多的规划和设计，进行金属填充。 在设计和布局期间，将导电迹线划分为有源和无源段可以在设计和布局期间识别器件内的关键或敏感器件元件的潜在负面影响。 以前，设计和布局后实施了金属填充，并且经常导致IC设计中以前未考虑的负面影响。 本发明的实施例减少了在设计和布局之后掺入金属填充物的其他装置中的劣化。 另外，因为在IC的设计和布局期间考虑了非活性金属填充段的物理特性。

公开(公告)号：US20060273874A1

公开(公告)日：2006-12-07

申请号：US11504073

申请日：2006-08-15

Applicant: Carol Barrett ,  Tom McKay ,  Subhas Bothra

Inventor： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC: H01F5/00

CPC classification number: H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

公开(公告)号：US07095307B1

公开(公告)日：2006-08-22

申请号：US10623084

申请日：2003-07-17

Applicant: Carol Barrett ,  Tom McKay ,  Subhas Bothra

Inventor： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC: H01F5/00

CPC classification number: H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

公开(公告)号：US06492716B1

公开(公告)日：2002-12-10

申请号：US09846335

申请日：2001-04-30

Applicant: Subhas Bothra ,  Thomas G. McKay ,  Ravi Jhota

Inventor： Subhas Bothra ,  Thomas G. McKay ,  Ravi Jhota

IPC: H01L2302

CPC classification number: H01L23/564 ,  H01L23/552 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a seal ring which includes a plurality of cuts separating the seal ring into seal ring portions which are disposed adjacent to different circuits in the integrated circuit die. The cuts reduce the noise coupling among the different circuits through the seal ring. To further isolate the sensitive RF/analog circuits from the noise generated by the digital circuit, the seal ring may be electrically (for dc noise) isolated from the substrate. This is accomplished, for instance, by inserting a polysilicon layer and gate oxide between the seal ring and the substrate. In addition, an n-well/p-well capacitor may be formed in series with the gate oxide, for instance, by implanting an n-well below the polysilicon layer in a p-type substrate. In this way, the seal ring provides substantially reduced noise coupling among the circuits but still maintains an effective wall around the periphery of the die to protect the circuits against moisture and ionic contamination penetration.

Abstract translation: 本发明的实施例提供了一种密封环，其包括将密封环分隔成密封环部分的多个切口，所述密封环部分邻近集成电路管芯中的不同电路设置。 切割可以通过密封环减少不同电路之间的噪声耦合。 为了进一步将敏感的RF /模拟电路与数字电路产生的噪声隔离开，密封环可能是与基板隔离的电气（用于直流噪声）。 这通过例如在密封环和衬底之间插入多晶硅层和栅极氧化物来实现。 此外，n阱/ p阱电容器可以与栅极氧化物串联形成，例如通过在p型衬底中注入多晶硅层下面的n阱。 以这种方式，密封环在电路之间提供显着降低的噪声耦合，但仍然保持围绕芯片周边的有效壁，以保护电路免受潮湿和离子污染的渗透。