公开(公告)号：US4645955A

公开(公告)日：1987-02-24

申请号：US656091

申请日：1984-09-28

申请人： Katsunori Ueno

发明人： Katsunori Ueno

IPC分类号： G01C3/06 ,  G01C3/00 ,  G02B7/28 ,  G06T1/00 ,  H03K5/26 ,  H04N1/403

CPC分类号： H03K5/26

摘要： A signal conversion circuit is provided for obtaining quantized pattern data indicating a variation of photoelectric signal amplitudes along photosensor arrays by a variable pulse width signal indicating the amplitude of the photoelectric signal from each photosensor. A difference detector detects differences in pulse width of the variable pulse width signals to be compared to determine the extent of the variation with a predetermined unit precision. A comparison device determines whether or not the difference in pulse width exceeds a selected number of difference units and the pattern data indicating the variation are supplied only if the difference exceeds the selected number. Consequently, even if there are errors in the circuit elements constituting the signal conversion circuit, correct pattern data free from influence of such errors can be supplied. If the influence of an error on the circuit elements is to be compensated, a device is provided to determine the precision of the pattern data based on the purpose of the conversion circuit. Therefore, the precision of the pattern data can be kept at the highest possible level. The pulse width difference detector and the comparison device each operate as a quantizing system to convert the variable pulse width signal into a quantized signal at the same time so that it is not necessary to supplement the circuit with a circuit element for initiating operation.

摘要翻译： 提供信号转换电路，用于通过指示来自每个光电传感器的光电信号的幅度的可变脉冲宽度信号来获得指示沿着光电传感器阵列的光电信号幅度的变化的量化图案数据。 差分检测器检测要比较的可变脉冲宽度信号的脉冲宽度的差异，以确定具有预定单位精度的变化程度。 比较装置确定脉冲宽度差是否超过所选数量的差分单位，并且仅当差值超过所选数量时才提供指示变化的图形数据。 因此，即使在构成信号转换电路的电路元件中存在错误，也可以提供不受这种误差影响的正确图案数据。 如果误差对电路元件的影响被补偿，则提供一个设备，以根据转换电路的目的来确定模式数据的精度。 因此，图案数据的精度可以保持在最高水平。 脉冲宽度差检测器和比较装置各自作为量化系统进行操作，以将可变脉冲宽度信号同时转换为量化信号，使得不需要用电路元件来补充电路以启动操作。

公开(公告)号：US08836042B2

公开(公告)日：2014-09-16

申请号：US12539339

申请日：2009-08-11

申请人： Katsunori Ueno

发明人： Katsunori Ueno

IPC分类号： H01L27/06 ,  F02P11/02 ,  H03K17/082 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  F02P3/05 ,  H01L29/739 ,  H03K17/0812

CPC分类号： H01L29/0847 ,  F02P3/051 ,  F02P11/02 ,  H01L27/0623 ,  H01L27/0883 ,  H01L29/0696 ,  H01L29/7395 ,  H03K17/08128 ,  H03K17/0828

摘要： A semiconductor device includes an IGBT, a constant voltage circuit, and protection Zener diodes. The IGBT makes/breaks a low-voltage current flowing in a primary coil. The constant voltage circuit and the protection Zener diodes are provided between an external gate terminal and an external collector terminal. The constant voltage circuit supplies a constant gate voltage to the IGBT to thereby set a saturation current value of the IGBT to a predetermined limiting current value. The IGBT has the saturation current value in a limiting current value range of the semiconductor device.

摘要翻译： 半导体器件包括IGBT，恒压电路和保护齐纳二极管。 IGBT会使流过初级线圈的低压电流产生/断开。 恒压电路和保护齐纳二极管设置在外部栅极端子和外部集电极端子之间。 恒压电路向IGBT提供恒定的栅极电压，从而将IGBT的饱和电流值设定为规定的极限电流值。 IGBT在半导体器件的限制电流值范围内具有饱和电流值。

公开(公告)号：US08039346B2

公开(公告)日：2011-10-18

申请号：US12842116

申请日：2010-07-23

申请人： Katsunori Ueno

发明人： Katsunori Ueno

IPC分类号： H01L21/8236

CPC分类号： H01L29/66068 ,  H01L29/1608 ,  H01L29/7722 ,  H01L29/7827

摘要： An insulated gate silicon carbide semiconductor device is provided having small on-resistance in a structure obtained by combining the SIT and MOSFET structures having normally-off operation. The device includes an n− semiconductor layer on an SiC n+ substrate, a p-type base region and highly doped p-region both buried in the layer, a trench from the semiconductor layer surface to the p-base region, an n+ first source region in the surface of a p-type base region at the bottom of the trench, a p-type channel region in the surface of the sidewall of the trench, one end of which contacts the first source region, a gate electrode contacting the trench-side surface of the channel region via a gate insulating film, and a source electrode contacting the trench-side surface of the gate electrode via an interlayer insulating film and contacting the exposed first source region and p-base region at the bottom of the trench.

摘要翻译： 提供了一种绝缘栅极碳化硅半导体器件，其通过组合具有常关断操作的SIT和MOSFET结构而获得的结构中具有小的导通电阻。 该器件包括在SiC n +衬底上的n-半导体层，两个埋在该层中的p型基极区域和高掺杂p区域，从半导体层表面到p基极区域的沟槽，n +第一源极 在沟槽底部的p型基极区域的表面中的沟槽区域，沟槽侧壁的表面中的一个p型沟道区域，其一端接触第一源极区域，与栅极接触的栅电极 经栅极绝缘膜形成沟道区的侧表面，以及源电极，经由层间绝缘膜与栅电极的沟槽侧表面接触，并与沟槽底部的暴露的第一源区和p基区接触 。

公开(公告)号：US07982524B2

公开(公告)日：2011-07-19

申请号：US12131026

申请日：2008-05-30

申请人： Yuichi Harada ,  Yoshihiro Ikura ,  Yasumasa Watanabe ,  Katsunori Ueno

发明人： Yuichi Harada ,  Yoshihiro Ikura ,  Yasumasa Watanabe ,  Katsunori Ueno

IPC分类号： H03L5/00

CPC分类号： H01L27/0922 ,  H01L27/0222 ,  H01L27/0288 ,  H01L27/0629 ,  H01L27/1203 ,  H01L28/20

摘要： A level shift circuit and a semiconductor device are configured to prevent failure and malfunction even when an excessive negative voltage or ESD surge are applied to a high-voltage power supply terminal. The level shift circuit includes a level shift resistor, a current-limiting resistor connected in series to the level shift resistor, and an n-channel MOSFET, with its drain connected to the current-limiting resistor. An output of the level-up circuit is obtained from the positioned between the level shift resistor and the current-limiting resistor. By providing the current-limiting resistor, the current that flows due to an excessive negative voltage or ESD surge is suppressed to prevent the level shift circuit from failing or malfunctioning.

摘要翻译： 电平移位电路和半导体器件被配置为即使当过高的负电压或ESD浪涌被施加到高压电源端子时也防止故障和故障。 电平移位电路包括电平移位电阻器，与电平移位电阻器串联连接的限流电阻器和n沟道MOSFET，其漏极连接到限流电阻器。 电平转换电路的输出从位于电平移位电阻和限流电阻之间获得。 通过设置限流电阻，抑制由于过大的负电压或ESD浪涌而流动的电流，以防止电平移位电路发生故障或故障。

公开(公告)号：US07947600B2

公开(公告)日：2011-05-24

申请号：US12109335

申请日：2008-04-24

申请人： Masanobu Iwaya ,  Reiko Hiruta ,  Katsunori Ueno ,  Kunio Mochizuki

发明人： Masanobu Iwaya ,  Reiko Hiruta ,  Katsunori Ueno ,  Kunio Mochizuki

IPC分类号： H01L21/44

CPC分类号： H01F27/2804 ,  H01F2027/2809 ,  H01L23/5227 ,  H01L23/60 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/00

摘要： A micro-transformer manufacturing method is provided, which can improve throughput, prevent a crack from entering an insulating film between coils, and manufacture the micro-transformer without using a mask material having a high selection ratio. An insulating film is deposited on the whole face of a semiconductor substrate having an impurity-diffused region. This insulating film is partially removed to form a first opening and a second opening. A primary coil is formed such that a center pad contacts the impurity-diffused region through the first opening. A thin insulating film is deposited on the primary coil. An insulator material having a secondary coil formed thereon is adhered onto the insulating film on the primary coil by adhesive tape. The insulator material is sized to not cover both a pad, connected with the center pad of the primary coil through the impurity-diffused region, and an outer-end pad of the primary coil.

摘要翻译： 提供一种微型变压器制造方法，其可以提高生产率，防止裂纹进入线圈之间的绝缘膜，并且在不使用具有高选择率的掩模材料的情况下制造微型变压器。 绝缘膜沉积在具有杂质扩散区域的半导体衬底的整个面上。 该绝缘膜被部分去除以形成第一开口和第二开口。 初级线圈形成为使得中心焊盘通过第一开口接触杂质扩散区域。 初级线圈上沉积有薄的绝缘膜。 其上形成有次级线圈的绝缘体材料通过胶带粘附在初级线圈上的绝缘膜上。 绝缘体材料的尺寸设计成不覆盖通过杂质扩散区域与初级线圈的中心焊盘连接的焊盘和初级线圈的外端焊盘。

公开(公告)号：US20060253225A1

公开(公告)日：2006-11-09

申请号：US11347568

申请日：2006-02-06

申请人： Katsunori Ueno ,  Tomoya Takahashi ,  Makoto Umeki

发明人： Katsunori Ueno ,  Tomoya Takahashi ,  Makoto Umeki

IPC分类号： G05D3/12

CPC分类号： H02J4/00 ,  Y04S20/224

摘要： In an operational control device 20 of a power supply system for supplying electric power from an electric power equipment 4 to a plurality of power consumption systems 8A to 8F, a power consumption pattern of each of the power consumption systems is stored, and a combined expected power consumption pattern 40 is obtained by adding together power consumption patterns of operating power consumption systems. Next, a combined assumed power consumption pattern is obtained by adding a power consumption pattern, obtained based on a temporary operational start time, of a power consumption system which has made the request for starting operation to the combined expected power consumption pattern. Subsequently, the combined assumed power consumption pattern and a preset allowable power 42 of the power supply equipment are compared to each other, and the temporary operational start time of the power consumption pattern is delayed along the axis of time until each of the power values in the combined assumed power consumption pattern is no longer above the preset allowable power. Thereafter, an expected operational start time is decided based on the temporary operational start time at which all power values represented in the combined assumed power consumption pattern are smaller than the preset allowable power, and an operational permission signal is outputted when the current time reaches the decided expected operational start time.

摘要翻译： 在从电力设备4向多个电力消耗系统8A〜8F供电的供电系统的运转控制装置20中，存储有各功率消耗系统的功耗模式， 组合的预期功耗模式40通过将工作功耗系统的功耗模式相加而获得。 接下来，通过将已经进行了开始运行请求的功耗系统的基于临时运行开始时间获得的功耗模式与组合的预期功耗模式相加来获得组合的假想功耗模式。 随后，将组合的假设功耗模式和电源设备的预设容许功率42相互比较，并且功耗模式的临时操作开始时间沿时间轴延迟，直到每个功率值在 组合的假设功耗模式不再高于预设容许功率。 此后，基于组合的假想功耗模式中表示的所有功率值小于预设容许功率的临时操作开始时间来决定预期操作开始时间，并且当当前时间到达时输出操作许可信号 决定预计运营开始时间。

公开(公告)号：US07098488B2

公开(公告)日：2006-08-29

申请号：US10839791

申请日：2004-05-05

申请人： Koh Yoshikawa ,  Katsunori Ueno ,  Hiroshi Kanemaru

发明人： Koh Yoshikawa ,  Katsunori Ueno ,  Hiroshi Kanemaru

IPC分类号： H01L29/73

CPC分类号： H01L29/41741 ,  H01L29/7397

摘要： An IGBT having a trench gate structure is disclosed which generates decreased noise at switching and displays superiority in saturation voltage to turn-off loss characteristics (trade-off characteristics). In a part of a region on an emitter side surface interposed between trench gates, a sub well region is provided, which is connected to an emitter electrode through diodes. When the IGBT is in a turned-on state, the diodes are brought into a non-conduction state to isolate the sub well region from the emitter electrode, by which carriers are accumulated. When the IGBT is in a turned-off state, the diodes are brought into a conduction state to electrically connect the sub well region to the emitter electrode, by which carriers are discharged at a high speed. In an early stage of turning-on of the IGBT, capacitance of a portion of the gate facing the sub well region is converted to gate-emitter capacitance to thereby reduce gate-collector capacitance, by which electromagnetic noise at switching is reduced.

摘要翻译： 公开了具有沟槽栅极结构的IGBT，其在开关时产生降低的噪声，并且将饱和电压的优越性显示为关断损耗特性（权衡特性）。 在介于沟槽栅极之间的发射极侧表面的区域的一部分中，设置有通过二极管连接到发射极的子阱区域。 当IGBT处于导通状态时，二极管进入非导通状态，以将子阱区域与发射极隔离，由此累积载流子。 当IGBT处于关断状态时，二极管进入导通状态，以将子阱区域电连接到发射极电极，载流子以高速放电。 在IGBT的导通的早期阶段，面向子阱区域的栅极的一部分的电容被转换为栅极 - 发射极电容，从而减小栅极 - 集电极电容，由此降低开关中的电磁噪声。

公开(公告)号：US6117735A

公开(公告)日：2000-09-12

申请号：US225171

申请日：1999-01-05

申请人： Katsunori Ueno

发明人： Katsunori Ueno

IPC分类号： H01L21/04 ,  H01L21/336 ,  H01L21/337 ,  H01L29/12 ,  H01L29/24 ,  H01L29/772 ,  H01L29/78 ,  H01L29/808 ,  H01L21/3205

CPC分类号： H01L29/66598 ,  H01L21/0465 ,  H01L29/66068 ,  H01L29/7722 ,  H01L29/7827 ,  H01L29/8083 ,  H01L29/1608

摘要： In a method for forming a silicon carbide vertical FET, a first mask and a second mask that overlaps the first mask are used so that a first conductivity type impurity region is defined by one end of a certain portion of the first mask, and that portion of the first mask and the second mask are then removed so that a second conductivity type impurity region is defined by another portion of the first mask. Thus, the first conductivity type impurity region and the second conductivity type impurity region are positioned relative to each other, with respect to the first mask. If a mask including a tapered end portion is used, and ion implantation is conducted with different accelerating-field voltages, the first conductivity type region and the second conductivity type region may be formed by self-alignment, using only one mask. By controlling the impurity concentration of the channel region, the threshold voltage can be controlled, and a normally-off type FET can be provided.

摘要翻译： 在形成碳化硅垂直FET的方法中，使用与第一掩模重叠的第一掩模和第二掩模，使得第一导电型杂质区域由第一掩模的某一部分的一端限定，并且该部分 然后去除第一掩模和第二掩模，使得第二导电型杂质区域由第一掩模的另一部分限定。 因此，第一导电型杂质区域和第二导电型杂质区域相对于第一掩模相对于彼此定位。 如果使用包括锥形端部的掩模，并且以不同的加速场电压进行离子注入，则可以仅使用一个掩模，通过自对准来形成第一导电类型区域和第二导电类型区域。 通过控制沟道区域的杂质浓度，可以控制阈值电压，并且可以提供常关型FET。

公开(公告)号：US5844760A

公开(公告)日：1998-12-01

申请号：US1199

申请日：1993-01-07

申请人： Naoki Kumagai ,  Katsunori Ueno

发明人： Naoki Kumagai ,  Katsunori Ueno

IPC分类号： G05F1/569 ,  H01L27/02 ,  H03K17/082 ,  H02H9/00

CPC分类号： H03K17/0822 ,  G05F1/569 ,  H01L27/0248

摘要： An insulated-gate controlled semiconductor device includes a main circuit that is controlled by an insulated gate having a gate resistor, an overload detector having the insulated gate for use in common with the main circuit, the overload detector being of the same construction as that of the main circuit, a current detector for detecting current passing through the overload detector, and a field effect transistor having a gate which responds to the voltage drop across the current detector. The main circuit is protected by lowering the voltage applied to the insulated gate through the gate resistor and through the low on-resistance of the field effect transistor while the field effect transistor is held on.

摘要翻译： 绝缘栅控制半导体器件包括由具有栅极电阻器的绝缘栅极控制的主电路，具有与主电路共同使用的绝缘栅极的过载检测器，过载检测器具有与 主电路，用于检测通过过载检测器的电流的电流检测器，以及具有响应于电流检测器上的电压降的栅极的场效应晶体管。 通过栅极电阻降低施加到绝缘栅极的电压，并通过场效应晶体管的低导通电阻来保护主电路，同时场效应晶体管被保持。

公开(公告)号：US5693569A

公开(公告)日：1997-12-02

申请号：US768807

申请日：1996-12-18

申请人： Katsunori Ueno

发明人： Katsunori Ueno

IPC分类号： H01L21/04 ,  H01L29/12 ,  H01L29/24 ,  H01L29/47 ,  H01L29/78 ,  H01L21/44 ,  H01L21/20

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7806 ,  H01L29/1608 ,  H01L29/47 ,  Y10S438/931

摘要： A silicon carbide trench MOSFET is provided that includes a first conductivity type semiconductor substrate made of silicon carbide. A first conductivity type drift layer and a second conductivity type base layer, both made of silicon carbide, are sequentially formed by epitaxial growth on the semiconductor substrate. The first conductivity type drift layer has a lower impurity concentration than the semiconductor substrate. A first conductivity type source region is formed in a part of a surface layer of the second conductivity type base layer. A gate electrode is received through an insulating film, in a first trench extending from a surface of the first conductivity type source region to reach the first conductivity type drift layer. A Schottky electrode disposed on an inner surface of a second trench having a greater depth than the first trench.

摘要翻译： 提供了一种碳化硅沟槽MOSFET，其包括由碳化硅制成的第一导电类型的半导体衬底。 通过外延生长在半导体衬底上顺序地形成由碳化硅制成的第一导电型漂移层和第二导电型基极层。 第一导电型漂移层的杂质浓度比半导体衬底低。 第一导电型源极区域形成在第二导电型基极层的表面层的一部分中。 在从第一导电类型源区的表面延伸到第一导电类型漂移层的第一沟槽中，通过绝缘膜接收栅电极。 肖特基电极设置在具有比第一沟槽更大的深度的第二沟槽的内表面上。