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公开(公告)号：US07982524B2
公开(公告)日：2011-07-19
申请号：US12131026
申请日：2008-05-30
IPC分类号： H03L5/00
CPC分类号： H01L27/0922 , H01L27/0222 , H01L27/0288 , H01L27/0629 , H01L27/1203 , H01L28/20
摘要： A level shift circuit and a semiconductor device are configured to prevent failure and malfunction even when an excessive negative voltage or ESD surge are applied to a high-voltage power supply terminal. The level shift circuit includes a level shift resistor, a current-limiting resistor connected in series to the level shift resistor, and an n-channel MOSFET, with its drain connected to the current-limiting resistor. An output of the level-up circuit is obtained from the positioned between the level shift resistor and the current-limiting resistor. By providing the current-limiting resistor, the current that flows due to an excessive negative voltage or ESD surge is suppressed to prevent the level shift circuit from failing or malfunctioning.
摘要翻译： 电平移位电路和半导体器件被配置为即使当过高的负电压或ESD浪涌被施加到高压电源端子时也防止故障和故障。 电平移位电路包括电平移位电阻器，与电平移位电阻器串联连接的限流电阻器和n沟道MOSFET，其漏极连接到限流电阻器。 电平转换电路的输出从位于电平移位电阻和限流电阻之间获得。 通过设置限流电阻，抑制由于过大的负电压或ESD浪涌而流动的电流，以防止电平移位电路发生故障或故障。
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公开(公告)号：US20070029636A1
公开(公告)日：2007-02-08
申请号：US11420779
申请日：2006-05-29
IPC分类号： H01L29/00
CPC分类号： H01L21/76283 , H01L21/76275 , H01L21/823878 , H01L21/84 , H01L27/12 , H01L29/78603
摘要： The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-semiconductor substrate is in contact with the insulating isolation region to allow an excellent breakdown voltage to be obtained. Moreover, by forming a high impurity concentration region such as a field-stop layer on the back surface of the n-semiconductor substrate, a depletion layer extending from the top surface is prevented from reaching the back surface This eliminates an influence of a surface state introduced in the interface between the insulator film formed on the back surface and the n-semiconductor substrate, by which an excellent breakdown voltage can be obtained.
摘要翻译： 绝缘隔离区域的绝缘材料的顶端的形状设置为在n半导体衬底的背面下方凹入的凹部。 这降低了在半导体衬底的底部与绝缘隔离区接触的拐角处的电场强度，以获得优异的击穿电压。 此外，通过在n半导体衬底的背面上形成诸如场阻止层的高杂质浓度区域，可以防止从顶面延伸的耗尽层到达后表面。这消除了表面状态的影响 引入到形成在背面的绝缘体膜与n半导体衬底之间的界面中，由此可以获得优异的击穿电压。
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公开(公告)号：US07723817B2
公开(公告)日：2010-05-25
申请号：US11420779
申请日：2006-05-29
IPC分类号： H01L29/00
CPC分类号： H01L21/76283 , H01L21/76275 , H01L21/823878 , H01L21/84 , H01L27/12 , H01L29/78603
摘要： The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-semiconductor substrate is in contact with the insulating isolation region to allow an excellent breakdown voltage to be obtained. Moreover, by forming a high impurity concentration region such as a field-stop layer on the back surface of the n-semiconductor substrate, a depletion layer extending from the top surface is prevented from reaching the back surface. This eliminates an influence of a surface state introduced in the interface between the insulator film formed on the back surface and the n-semiconductor substrate, by which an excellent breakdown voltage can be obtained.
摘要翻译： 绝缘隔离区域的绝缘材料的顶端的形状设置为在n半导体衬底的背面下方凹入的凹部。 这降低了在半导体衬底的底部与绝缘隔离区接触的拐角处的电场强度，以获得优异的击穿电压。 此外，通过在n半导体衬底的背面上形成诸如场阻止层的高杂质浓度区域，可以防止从顶面延伸的耗尽层到达背面。 这消除了在形成在背面的绝缘体膜与n型半导体衬底之间的界面中引入的表面状态的影响，由此可获得优异的击穿电压。
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公开(公告)号：US20060027863A1
公开(公告)日：2006-02-09
申请号：US11196528
申请日：2005-08-03
IPC分类号： H01L29/76
CPC分类号： H01L29/7816 , H01L21/266 , H01L29/0878 , H01L29/0886 , H01L29/42368 , H01L29/66681
摘要： A lateral MOSFET and a method of forming thereof includes a p-type semiconductor substrate, a first n-type well in the surface portion of the semiconductor substrate, an n+-type drain region in the first n-type well, a p-type well in the first n-type well, an n+-type source region in the p-type well, a gate oxide film on the portion of the p-type well between the n+-type source region and the first n-type well, a gate electrode on the gate oxide film, and a second n-type well containing the p-type well therein to increase the n-type impurity concentration in the vicinity of the junction between the p-type well and the first n-type well beneath the gate and to increase the impurity amount and the thickness of the n-type semiconductor region beneath the p-type well. The first and second n-type wells can be overlapping or formed continuous or contiguous with each other. The lateral MOSFET exhibits a high punch-through breakdown voltage suitable for a high-side switch.
摘要翻译： 横向MOSFET及其形成方法包括p型半导体衬底，半导体衬底的表面部分中的第一n型阱，第一n型n型阱中的n + 型阱，p型阱中的第一n型阱中的p型阱，p型阱中的n + + +型源极区，p型阱部分中的栅极氧化膜 在n + +型源极区域和第一n型阱之间，栅极氧化物膜上的栅极电极以及其中包含p型阱的第二n型阱，以增加 在p型阱和栅极下面的第一n型阱之间的接合点附近的n型杂质浓度增加，并且增加p型阱下面的n型半导体区的杂质量和厚度。 第一和第二n型阱可以重叠或形成为彼此连续或连续的。 横向MOSFET表现出适合于高侧开关的高穿孔击穿电压。
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5.发明授权Surge voltage protection diode with controlled p-n junction density gradients 有权具有受控p-n结密度梯度的浪涌电压保护二极管公开(公告)号：US07602022B2
公开(公告)日：2009-10-13
申请号：US11374420
申请日：2006-03-14
IPC分类号： H01L23/62
CPC分类号： H01L27/0255 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： To prevent the destruction of a semiconductor element due to negative resistance, and to reduce the dynamic resistance of a static electricity prevention diode, the ratio of the maximum electric field intensity during an avalanche and the average electric field in a strong electric field region, as well as the impurity density gradient in the vicinity of the strong electric field region are optimized. During avalanche breakdown, a depletion layer is formed across the entire high resistivity region, and its average electric field is kept to ½ or more of the maximum electric field intensity. The density gradients (the depths and impurity densities) of a p+ region and of an n+ region that form a p-n junction of the diode are controlled so that the density gradient in the neighborhood of the high resistivity region does not have negative resistance with respect to increase of the avalanche current.
摘要翻译： 为了防止由于负电阻而导致的半导体元件的破坏，并且为了降低静电防护二极管的动态电阻，在雪崩期间的最大电场强度与强电场区域中的平均电场的比例，如 而且强电场区附近的杂质浓度梯度被优化。 在雪崩击穿期间，在整个高电阻率区域形成耗尽层，其平均电场保持在最大电场强度的1/2以上。 控制形成二极管的pn结的p +区域和n +区域的密度梯度（深度和杂质浓度），使得高电阻率区域附近的密度梯度相对于 增加雪崩电流。
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公开(公告)号：US20050145975A1
公开(公告)日：2005-07-07
申请号：US11054856
申请日：2005-02-10
申请人： Naoki Kumagai , Yuuichi Harada , Shinichi Jimbo , Yoshihiro Ikura , Tatsuhiko Fujihira , Kazuhiko Yoshida
发明人： Naoki Kumagai , Yuuichi Harada , Shinichi Jimbo , Yoshihiro Ikura , Tatsuhiko Fujihira , Kazuhiko Yoshida
IPC分类号： H01L29/872 , H01L21/822 , H01L21/8234 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/07 , H01L27/088 , H01L29/10 , H01L29/47 , H01L29/78 , H01L29/94
CPC分类号： H01L27/0255 , H01L27/0727 , H01L29/1087 , H01L29/47 , H01L29/7835
摘要： A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.
摘要翻译： 半导体器件被配置为当在单个芯片上形成桥接电路的MOSFET时，通过由寄生晶体管产生的寄生效应来防止元件的损坏和/或错误操作。 通过在横向MOSFET的源极区，漏极区和p阱区的n阱区域中设置阳极电极形成肖特基结。 构成多数载波器件的肖特基势垒二极管与能够正向偏置的PN结并联连接，使得PN结不被正向偏置，从而不产生少数载流子，从而抑制寄生效应。
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公开(公告)号：US07436024B2
公开(公告)日：2008-10-14
申请号：US11196528
申请日：2005-08-03
IPC分类号： H01L29/94
CPC分类号： H01L29/7816 , H01L21/266 , H01L29/0878 , H01L29/0886 , H01L29/42368 , H01L29/66681
摘要： A lateral MOSFET and a method of forming thereof includes a p-type semiconductor substrate, a first n-type well in the surface portion of the semiconductor substrate, an n+-type drain region in the first n-type well, a p-type well in the first n-type well, an n+-type source region in the p-type well, a gate oxide film on the portion of the p-type well between the n+-type source region and the first n-type well, a gate electrode on the gate oxide film, and a second n-type well containing the p-type well therein to increase the n-type impurity concentration in the vicinity of the junction between the p-type well and the first n-type well beneath the gate and to increase the impurity amount and the thickness of the n-type semiconductor region beneath the p-type well. The first and second n-type wells can be overlapping or formed continuous or contiguous with each other. The lateral MOSFET exhibits a high punch-through breakdown voltage suitable for a high-side switch.
摘要翻译： 横向MOSFET及其形成方法包括p型半导体衬底，半导体衬底的表面部分中的第一n型阱，第一n型n型阱中的n + 型阱，p型阱中的第一n型阱中的p型阱，p型阱中的n + + +型源极区，p型阱部分中的栅极氧化膜 在n + +型源极区域和第一n型阱之间，栅极氧化物膜上的栅极电极以及其中包含p型阱的第二n型阱，以增加 在p型阱和栅极下面的第一n型阱之间的接合点附近的n型杂质浓度增加，并且增加p型阱下面的n型半导体区的杂质量和厚度。 第一和第二n型阱可以重叠或形成为彼此连续或连续的。 横向MOSFET表现出适合于高侧开关的高穿孔击穿电压。
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公开(公告)号：US08362549B2
公开(公告)日：2013-01-29
申请号：US12974189
申请日：2010-12-21
申请人： Yoshihiro Ikura
发明人： Yoshihiro Ikura
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/66666 , H01L21/26586 , H01L29/1095 , H01L29/41766 , H01L29/66348 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要： A trench gate semiconductor device is disclosed which has a trench gate structure including an insulator in the upper portion of a first trench, the insulator being on a gate electrode; a source region having a lower end surface positioned lower than the upper surface of the gate electrode; a second trench in the surface portion of a semiconductor substrate between the first trenches, the second trench having a slanted inner surface providing the second trench with the widest trench width at its opening and a bottom plane positioned lower than the lower end surface of the source region, the slanted inner surface being in contact with the source region; and a p-type body-contact region in contact with the slanted inner surface of the second trench. The trench gate semiconductor device and its manufacturing method facilitate increasing the channel density and lowering the body resistance of the parasitic BJT.
摘要翻译： 公开了一种沟槽栅极半导体器件，其具有在第一沟槽的上部包括绝缘体的沟槽栅极结构，绝缘体位于栅电极上; 源极区域，其具有位于比栅极电极的上表面低的端面; 在所述第一沟槽之间的半导体衬底的表面部分中的第二沟槽，所述第二沟槽具有倾斜的内表面，所述第二沟槽在其开口处提供具有最宽沟槽宽度的第二沟槽和位于所述源极的下端表面下方的底平面 所述倾斜内表面与所述源区域接触; 以及与第二沟槽的倾斜内表面接触的p型体接触区域。 沟槽栅极半导体器件及其制造方法有利于增加通道密度并降低寄生BJT的体电阻。
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公开(公告)号：US07476935B2
公开(公告)日：2009-01-13
申请号：US11054856
申请日：2005-02-10
申请人： Naoki Kumagai , Yuuichi Harada , Shinichi Jimbo , Yoshihiro Ikura , Tatsuhiko Fujihira , Kazuhiko Yoshida
发明人： Naoki Kumagai , Yuuichi Harada , Shinichi Jimbo , Yoshihiro Ikura , Tatsuhiko Fujihira , Kazuhiko Yoshida
IPC分类号： H01L29/78
CPC分类号： H01L27/0255 , H01L27/0727 , H01L29/1087 , H01L29/47 , H01L29/7835
摘要： A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.
摘要翻译： 半导体器件被配置为当在单个芯片上形成桥接电路的MOSFET时，通过由寄生晶体管产生的寄生效应来防止元件的损坏和/或错误操作。 通过在横向MOSFET的源极区，漏极区和p阱区的n阱区域中设置阳极电极形成肖特基结。 构成多数载波器件的肖特基势垒二极管与能够正向偏置的PN结并联连接，使得PN结不被正向偏置，从而不产生少数载流子，从而抑制寄生效应。
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公开(公告)号：US20060231836A1
公开(公告)日：2006-10-19
申请号：US11374420
申请日：2006-03-14
IPC分类号： H01L29/04
CPC分类号： H01L27/0255 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： To prevent the destruction of a semiconductor element due to negative resistance, and to reduce the dynamic resistance of a static electricity prevention diode, the ratio of the maximum electric field intensity during an avalanche and the average electric field in a strong electric field region, as well as the impurity density gradient in the vicinity of the strong electric field region are optimized. During avalanche breakdown, a depletion layer is formed across the entire high resistivity region, and its average electric field is kept to ½ or more of the maximum electric field intensity. The density gradients (the depths and impurity densities) of a p+ region and of an n+ region that form a p-n junction of the diode are controlled so that the density gradient in the neighborhood of the high resistivity region does not have negative resistance with respect to increase of the avalanche current.
摘要翻译： 为了防止由于负电阻而导致的半导体元件的破坏，并且为了降低静电防护二极管的动态电阻，在雪崩期间的最大电场强度与强电场区域中的平均电场的比例，如 而且强电场区附近的杂质浓度梯度被优化。 在雪崩击穿期间，在整个高电阻率区域形成耗尽层，其平均电场保持在最大电场强度的1/2以上。 控制形成二极管的pn结的ap + SUP区域和n + SUP区域的密度梯度（深度和杂质浓度），使得密度梯度 相对于雪崩电流的增加，高电阻率区域的附近没有负电阻。
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