公开(公告)号：US06274483B1

公开(公告)日：2001-08-14

申请号：US09483933

申请日：2000-01-18

申请人： Weng Chang ,  Ying-Ho Chen ,  Syun-Ming Jang

发明人： Weng Chang ,  Ying-Ho Chen ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/76804 ,  H01L21/7688

摘要： A new method is provided for the creation of the trenches or line patterns of damascene structures. Under the first embodiment of the invention, the trenches that are created for the copper interconnect lines are sputter etched as a result of which the corners of the trenches around the top elevation of the trenches are rounded. Under the second embodiment of the invention a disposable hard mask is created over the surface of the dielectric after which the trenches for the interconnect lines are created. The surface of the hard mask layer including the created trenches are rf sputter etched resulting in a sharp reduction of the angle of incidence between sidewalls of the trenches around the perimeter of the trenches and the surface of the layer of dielectric. The barrier and seed layers are deposited over the surface of the disposable hard mask including the created trenches, the deposited copper is polished down to the surface of the dielectric.

摘要翻译： 提供了一种用于创建大马士革结构的沟槽或线条图案的新方法。 在本发明的第一实施例中，为铜互连线创建的沟槽被溅射蚀刻，结果，沟槽顶部高度周围的沟槽的角部是圆形的。 在本发明的第二实施例中，在电介质的表面上形成一次性硬掩模，之后形成用于互连线的沟槽。 包括产生的沟槽的硬掩模层的表面被溅射蚀刻，导致围绕沟槽的周边和电介质层的表面的沟槽的侧壁之间的入射角的急剧减小。 阻挡层和种子层沉积在包括所产生的沟槽的一次性硬掩模的表面上，沉积的铜被抛光到电介质的表面。

公开(公告)号：US20060112971A1

公开(公告)日：2006-06-01

申请号：US10999277

申请日：2004-11-30

申请人： Han-Hsin Kuo ,  Hsin-Hsien Lu ,  Ying-Ho Chen ,  Syun-Ming Jang

发明人： Han-Hsin Kuo ,  Hsin-Hsien Lu ,  Ying-Ho Chen ,  Syun-Ming Jang

IPC分类号： C23G1/00 ,  B08B7/00 ,  B08B3/00

CPC分类号： H01L21/02074 ,  C23G1/00

摘要： A method for cleaning a semiconductor wafer surface comprises sweeping the semiconductor wafer surface and applying a first cleaning solution having a first pH, stop applying the first cleaning solution and applying a first rinsing solution to the semiconductor wafer surface, the first rinsing solution having a second pH that is significantly different from the first pH, sweeping the semiconductor wafer surface and applying a second cleaning solution having a third pH, and stop applying the second cleaning solution and applying a second rinsing solution to the semiconductor wafer surface, the second rinsing solution having a fourth pH that is significantly different from the third pH.

摘要翻译： 一种清洗半导体晶片表面的方法，包括扫描半导体晶片表面并施加具有第一pH值的第一清洗溶液，停止施加第一清洗溶液并向半导体晶片表面施加第一冲洗溶液，第一冲洗溶液具有第二 pH与第一pH显着不同，扫描半导体晶片表面并施加具有第三pH的第二清洗溶液，并停止施加第二清洗溶液并将第二冲洗溶液施加到半导体晶片表面，第二冲洗溶液具有 与第三pH显着不同的第四个pH。

公开(公告)号：US06930040B2

公开(公告)日：2005-08-16

申请号：US10691019

申请日：2003-10-22

申请人： Chuan-Ping Hou ,  Syun-Ming Jang ,  Ying-Ho Chen ,  Tung-Ching Tseng

发明人： Chuan-Ping Hou ,  Syun-Ming Jang ,  Ying-Ho Chen ,  Tung-Ching Tseng

IPC分类号： H01L21/00 ,  H01L21/306 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/74 ,  H01L21/762

CPC分类号： H01L21/743 ,  H01L21/76283 ,  H01L21/76286

摘要： In a method of the present invention, an intermediate structure having a top surface is provided. An isolation trench is formed is the intermediate structure. Isolation material is deposited over the intermediate structure. The isolation material fills the isolation trench. Excess isolation material extends above the top surface of the intermediate structure. Part of the excess isolation material is removed until there is a predetermined thickness of isolation material remaining on the top surface of the intermediate structure. A contact opening is formed in the isolation material at the isolation trench. The contact opening extends through at least part of the intermediate structure. Contact material is deposited over the isolation material. The contact material fills the contact opening. Excess contact material, if any, that extends above the isolation material is removed. The excess isolation material is removed at least until the top surface of the intermediate structure is reached.

公开(公告)号：US20050106872A1

公开(公告)日：2005-05-19

申请号：US10714985

申请日：2003-11-17

申请人： William Hong ,  Chia-Che Chuang ,  Chi-Wei Chung ,  Wen-Chih Chiou ,  Ying-Ho Chen ,  Syun-Ming Jang

发明人： William Hong ,  Chia-Che Chuang ,  Chi-Wei Chung ,  Wen-Chih Chiou ,  Ying-Ho Chen ,  Syun-Ming Jang

IPC分类号： B24B1/00 ,  H01L21/02 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/02074 ,  H01L21/02065 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/7684

摘要： An oxide polishing process that is part of a CMP process flow is disclosed. After a copper layer is polished at a first polishing station and a diffusion barrier layer is polished at a second polishing station, a key sequence at a third polish station is the application of a first oxide slurry and a first DI water rinse followed by a second oxide slurry and then a second DI water rinse. As a result, defect counts are reduced from several thousand to less than 100. Another important factor is a low down force that enables more efficient particle removal. The improved oxide polishing process has the same throughput as a single oxide polish and a DI water rinse method and may be implemented in any three slurry copper CMP process flow.

摘要翻译： 公开了作为CMP工艺流程的一部分的氧化物抛光工艺。 在第一抛光站抛光铜层并且在第二抛光站抛光扩散阻挡层之后，在第三抛光工位上的键序列是施加第一氧化物浆料和第一DI水冲洗，然后是第二抛光 氧化物浆液，然后用第二次DI水冲洗。 因此，缺陷计数从几千减少到小于100.另一个重要因素是能够更有效地除去颗粒的低下降力。 改进的氧化物抛光方法具有与单一氧化物抛光剂和DI水漂洗方法相同的生产量，并且可以在任何三种浆料铜CMP工艺流程中实施。

公开(公告)号：US06806184B2

公开(公告)日：2004-10-19

申请号：US10290630

申请日：2002-11-08

申请人： Ying-Ho Chen ,  Syun-Ming Jang

发明人： Ying-Ho Chen ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/76838 ,  H01L21/7684

摘要： A new method is provided for the creation of copper interconnects. An opening is created in a layer of dielectric, a layer of barrier material is deposited. The layer of barrier material extends over the surface of the layer of dielectric. A film of copper is deposited over the surface of the layer of barrier material. The copper film is polished down to the surface of the layer of barrier material, creating a first copper interconnect. The created first copper interconnect is subjected to a thermal anneal, inducing copper hillocks in the surface of the first copper interconnect by releasing copper film stress in the first copper interconnect. The copper hillocks are then removed by polishing the surface of the created first copper interconnect down to the surface of the surrounding layer of dielectric, creating a second and final copper interconnect.

摘要翻译： 提供了一种用于创建铜互连的新方法。 在电介质层中产生开口，沉积一层屏障材料。 阻挡材料层在电介质层的表面上延伸。 一层铜沉积在阻挡材料层的表面上。 铜膜被抛光到阻挡材料层的表面，形成第一铜互连。 所制造的第一铜互连件经受热退火，通过在第一铜互连中释放铜膜应力，在第一铜互连表面上引起铜小丘。 然后通过将所形成的第一铜互连的表面抛光到电介质周围的表面，去除铜小丘，产生第二和最后的铜互连。

公开(公告)号：US06544891B1

公开(公告)日：2003-04-08

申请号：US09945435

申请日：2001-09-04

申请人： Ying-Ho Chen ,  Wen-Chih Chiou ,  Tsu Shih ,  Syun-Ming Jang

发明人： Ying-Ho Chen ,  Wen-Chih Chiou ,  Tsu Shih ,  Syun-Ming Jang

IPC分类号： H01L2144

CPC分类号： H01L21/7684 ,  H01L21/76838

摘要： A method of copper metallization wherein copper flaking and metal bridging problems are eliminated by an annealing process is described. A first metal line is provided on an insulating layer overlying a semiconductor substrate. A dielectric stop layer is deposited overlying the first metal line. A dielectric layer is deposited overlying the dielectric stop layer. An opening is etched through the dielectric layer and the dielectric stop layer to the first metal line. A barrier metal layer is deposited over the surface of the dielectric layer and within the opening. A copper layer is deposited over the surface of the barrier metal layer. The copper layer and barrier metal layer not within the opening are polished away wherein after a time period, copper flakes form on the surface of the copper and dielectric layers. The copper layer and the dielectric layer are alloyed whereby the copper layer is stabilized and the copper flakes are removed to complete copper damascene metallization in the fabrication of an integrated circuit.

摘要翻译： 描述了通过退火工艺消除铜剥落和金属桥接问题的铜金属化方法。 第一金属线设置在覆盖在半导体衬底上的绝缘层上。 沉积在第一金属线上的电介质停止层。 介电层沉积在介电阻挡层上。 通过介电层和电介质停止层蚀刻开口到第一金属线。 阻挡金属层沉积在电介质层的表面上并且在开口内。 在阻挡金属层的表面上沉积铜层。 不在开口内的铜层和阻挡金属层被抛光，其中在一段时间之后，在铜和电介质层的表面上形成铜片。 将铜层和电介质层合金化，由此铜层稳定，并且在制造集成电路中去除铜片以完成铜镶嵌金属化。

公开(公告)号：US06518183B1

公开(公告)日：2003-02-11

申请号：US09947782

申请日：2001-09-06

申请人： Weng Chang ,  Tien-I Bao ,  Ying-Ho Chen ,  Syun-Ming Jang

发明人： Weng Chang ,  Tien-I Bao ,  Ying-Ho Chen ,  Syun-Ming Jang

IPC分类号： H01L2144

CPC分类号： H01L21/76883 ,  H01L21/76834

摘要： Within a method for fabricating a microelectronic fabrication having formed therein a copper containing conductor layer passivated with a passivation layer, there is first: (1) pre-heated the copper containing conductor layer to a temperature of from about 300 to about 450 degrees centigrade for a time period of from about 30 to about 120 seconds to form a pre-heated copper containing conductor layer; and then (2) plasma treated the pre-heated copper containing conductor layer within a reducing plasma to form a plasma treated pre-heated copper containing conductor layer; prior to (3)forming upon the plasma treated pre-heated copper containing conductor layer the passivation layer. The foregoing process sequence provides for attenuated hillock defects within the plasma treated pre-heated copper containing conductor layer when forming the passivation layer thereupon.

摘要翻译： 在其中形成有钝化层钝化的含铜导体层的微电子制造方法中，首先：（1）将含铜导体层预热至约300至约450摄氏度的温度，用于 约30至约120秒的时间段以形成预热的含铜导体层; 然后（2）在还原等离子体中等离子体处理预热的含铜导体层，以形成等离子体处理的预热含铜导体层; 在（3）在等离子体处理的预热含铜导体层上形成钝化层之前。 当在其上形成钝化层时，上述工艺顺序提供等离子体处理的预热含铜导体层内的衰减的小丘缺陷。

公开(公告)号：US06398627B1

公开(公告)日：2002-06-04

申请号：US09815427

申请日：2001-03-22

申请人： Wen-Chih Chiou ,  Ying-Ho Chen ,  Tsu Shih ,  Syun-Ming Jang

发明人： Wen-Chih Chiou ,  Ying-Ho Chen ,  Tsu Shih ,  Syun-Ming Jang

IPC分类号： B24B900

CPC分类号： B24B37/04 ,  B24B57/02

摘要： A slurry dispensing unit for a chemical mechanical polishing apparatus equipped with multiple slurry dispensing nozzles is disclosed. The slurry dispensing unit is constructed by a dispenser body that has a delivery conduit, a return conduit and a U-shape conduit connected in fluid communication therein between for flowing continuously a slurry solution therethrough and a plurality of nozzles integrally connected to and in fluid communication with a fluid passageway in the delivery conduit for dispensing a slurry solution. The multiple slurry dispensing nozzles may either have a fixed opening or adjustable openings by utilizing a flow control valve at each nozzle opening.

摘要翻译： 公开了一种用于配备有多个浆料分配喷嘴的化学机械抛光设备的浆料分配单元。 浆料分配单元由分配器主体构成，分配器主体具有输送管道，回流管道和连接在其中的流体连通的U形管道，用于连续地流动通过其中的浆液;以及多个喷嘴，其一体地连接到流体连通 在输送管道中具有用于分配浆液的流体通道。 多个浆料分配喷嘴可以通过在每个喷嘴开口处利用流量控制阀来具有固定的开口或可调节的开口。

公开(公告)号：US06194307B1

公开(公告)日：2001-02-27

申请号：US09298930

申请日：1999-04-26

申请人： Ying-Ho Chen ,  Syun-Ming Jang

发明人： Ying-Ho Chen ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/7684

摘要： After the first layer of copper has been deposited and polished (to form the pattern of copper damascene conducting lines) a layer of Ta or TaN/Cu is deposited. Another thin layer of copper is deposited thereby filling existing pores and recesses in the polished copper lines. A second CMP is applied to the surface of the second deposited layer of copper, this second CMP removes the redundant copper from the space where the Inter Metal Dielectric (IMD) layer will be created. Prior to the deposition of the second layer of copper, a (brief) etchback of the (surface of the) first layer of copper can be performed in order to enhance copper surface integrity and thereby improve the deposition of the second layer of copper. A layer of TaN/Ta and a layer of seed copper can be deposited within the openings for the damascene conducting lines prior to the deposition of these lines.

摘要翻译： 在第一层铜被沉积和抛光之后（形成铜镶嵌导电线的图案），沉积一层Ta或TaN / Cu。 沉积另一薄铜层，从而填充抛光铜线中的现有孔和凹槽。 第二CMP施加到第二沉积铜层的表面上，该第二CMP从产生金属间介质（IMD）层的空间中去除冗余铜。 在沉积第二层铜之前，可以执行铜（第一层）的（表面）的（简短的）回蚀，以便增强铜表面的完整性，从而改善第二层铜的沉积。 在沉积这些线之前，可以在用于镶嵌导电线的开口内沉积一层TaN / Ta和一层种子铜。

公开(公告)号：US07187084B2

公开(公告)日：2007-03-06

申请号：US10760905

申请日：2004-01-20

申请人： Syun-Ming Jang ,  Chung-Shi Liu ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76832 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/31127 ,  H01L21/31138 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/76807

摘要： A damascene structure is provided comprising a substrate, a lower intermetal dielectric layer over the substrate, an exposed conductive structure within the lower intermetal dielectric layer, a composite etch stop layer over the lower intermetal dielectric layer and the exposed conductive structure; the composite etch stop layer comprising a first lower sub-layer and a second upper sub-layer, an upper intermetal dielectric layer over the composite etch stop layer, a trench interconnection opening forming within the upper intermetal dielectric layer and the composite etch stop layer, the trench interconnection opening exposing the conductive structure, a barrier metal layer at least lining the trench interconnection opening. and a conductor plug within the trench interconnection opening, contacting the conductive structure. The upper surface of the barrier metal layer is coplanar with the upper surface of the conductor plug.

摘要翻译： 提供一种镶嵌结构，其包括基底，在该基底上的下部金属间电介质层，该下部金属间电介质层内的暴露的导电结构，该下部金属间介电层上的复合蚀刻停止层和该暴露的导电结构; 所述复合蚀刻停止层包括第一下部子层和第二上部子层，复合蚀刻停止层上方的上部金属间介电层，在上部金属间介电层和复合蚀刻停止层中形成的沟槽互连开口， 所述沟槽互连开口暴露所述导电结构，至少衬垫所述沟槽互连开口的阻挡金属层。 以及沟槽互连开口内的导体插头，与导电结构接触。 阻挡金属层的上表面与导体插塞的上表面共面。