公开(公告)号：US20060112971A1

公开(公告)日：2006-06-01

申请号：US10999277

申请日：2004-11-30

申请人： Han-Hsin Kuo ,  Hsin-Hsien Lu ,  Ying-Ho Chen ,  Syun-Ming Jang

发明人： Han-Hsin Kuo ,  Hsin-Hsien Lu ,  Ying-Ho Chen ,  Syun-Ming Jang

IPC分类号： C23G1/00 ,  B08B7/00 ,  B08B3/00

CPC分类号： H01L21/02074 ,  C23G1/00

摘要： A method for cleaning a semiconductor wafer surface comprises sweeping the semiconductor wafer surface and applying a first cleaning solution having a first pH, stop applying the first cleaning solution and applying a first rinsing solution to the semiconductor wafer surface, the first rinsing solution having a second pH that is significantly different from the first pH, sweeping the semiconductor wafer surface and applying a second cleaning solution having a third pH, and stop applying the second cleaning solution and applying a second rinsing solution to the semiconductor wafer surface, the second rinsing solution having a fourth pH that is significantly different from the third pH.

摘要翻译： 一种清洗半导体晶片表面的方法，包括扫描半导体晶片表面并施加具有第一pH值的第一清洗溶液，停止施加第一清洗溶液并向半导体晶片表面施加第一冲洗溶液，第一冲洗溶液具有第二 pH与第一pH显着不同，扫描半导体晶片表面并施加具有第三pH的第二清洗溶液，并停止施加第二清洗溶液并将第二冲洗溶液施加到半导体晶片表面，第二冲洗溶液具有 与第三pH显着不同的第四个pH。

公开(公告)号：US20050170980A1

公开(公告)日：2005-08-04

申请号：US10769245

申请日：2004-01-30

申请人： Hsin-Hsien Lu ,  Han-Hsin Kuo ,  Ying-Ho Chen ,  Syum-Ming Jang

发明人： Hsin-Hsien Lu ,  Han-Hsin Kuo ,  Ying-Ho Chen ,  Syum-Ming Jang

IPC分类号： C11D7/26 ,  C11D11/00 ,  H01L21/02 ,  C11D1/00

CPC分类号： C11D7/262 ,  C11D7/261 ,  C11D11/0047 ,  H01L21/02074

摘要： A method for the cleaning of wafers typically during a chemical mechanical polishing (CMP) process. The method includes polishing a material layer on a wafer in sequential polishing steps, rinsing the wafer using a novel surfactant composition solution after at least one of the polishing steps and rinsing of the wafer using deionized water, respectively. The surfactant composition solution imparts a generally hydrophilic character to a hydrophobic material layer such as a high-k dielectric layer on the wafer. Consequently, the layer is rendered amenable to cleaning by deionized water, thereby significantly enhancing the removal of particles from the layer and reducing the number of defects related to the CMP process.

摘要翻译： 通常在化学机械抛光（CMP）工艺期间清洗晶片的方法。 该方法包括在顺序抛光步骤中抛光晶片上的材料层，在至少一个抛光步骤和使用去离子水冲洗晶片之后，使用新型表面活性剂组合物溶液冲洗晶片。 表面活性剂组合物溶液对疏水性材料层（例如晶片上的高k电介质层）具有普遍的亲水性。 因此，该层适于用去离子水清洗，从而显着增强颗粒从层中的去除并减少与CMP工艺相关的缺陷数量。

公开(公告)号：US06962869B1

公开(公告)日：2005-11-08

申请号：US10270974

申请日：2002-10-15

申请人： Tien-I Bao ,  Hsin-Hsien Lu ,  Lih-Ping Li ,  Chung-Chi Ko ,  Aaron Song ,  Syun-Ming Jang

发明人： Tien-I Bao ,  Hsin-Hsien Lu ,  Lih-Ping Li ,  Chung-Chi Ko ,  Aaron Song ,  Syun-Ming Jang

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/3105 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835

摘要： A method of protecting a low k dielectric layer that is preferably comprised of a material containing Si, O, C, and H is described. The dielectric layer is subjected to a gas plasma that is generated from a CXHY gas which is preferably ethylene. Optionally, hydrogen may be added to the CXHY gas. Another alternative is a two step plasma process involving a first plasma treatment of CXHY or CXHY combined with H2 and a second plasma treatment with H2. The modified dielectric layer provides improved adhesion to anti-reflective layers and to a barrier metal layer in a damascene process. The modified dielectric layer also has a low CMP rate that prevents scratch defects and an oxide recess from occurring next to the metal layer on the surface of the damascene stack. The plasma treatments are preferably done in the same chamber in which the dielectric layer is deposited.

摘要翻译： 描述了保护低k电介质层的方法，其优选由含有Si，O，C和H的材料组成。 对电介质层进行气化等离子体，该等离子体是由优选乙烯的C X H Y气产生的。 任选地，可以将氢气加入到C 1 H 2 H 2 O气体中。 另一种替代方案是涉及第一等离子体处理C X> Y Y or SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB >与H 2 H 2结合，并且与H 2 2进行第二等离子体处理。 改进的介电层在镶嵌工艺中提供对抗反射层和阻挡金属层的改善的粘合性。 改进的介电层也具有低CMP速率，其防止划痕缺陷和氧化物凹陷在镶嵌层的表面上邻近金属层发生。 等离子体处理优选在沉积介电层的相同的室中进行。

公开(公告)号：US06677251B1

公开(公告)日：2004-01-13

申请号：US10207339

申请日：2002-07-29

申请人： Hsin-Hsien Lu ,  Aaron Song ,  Tien-I Bao ,  Syun-Ming Jang

发明人： Hsin-Hsien Lu ,  Aaron Song ,  Tien-I Bao ,  Syun-Ming Jang

IPC分类号： H01L2131

CPC分类号： H01L21/76826 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76814

摘要： A method for forming a dielectric insulating layer with increased hydrophilicity for improving adhesion of an adjacently deposited material layer in semiconductor device manufacturing including providing a semiconductor wafer having a process surface for forming a dielectric insulting layer thereover; depositing the dielectric insulating layer; and, subjecting the dielectric insulating layer including an exposed surface to a hydrophilicity increasing treatment including at least one of a dry plasma treatment and a wet process including contacting the exposed surface with a hydrophilicity increasing solution including a surfactant said wet process followed by a baking process to improve an adhesion of an adjacently deposited material layer.

摘要翻译： 一种用于形成具有增加的亲水性以提高相邻沉积材料层在半导体器件制造中的粘合性的介电绝缘层的方法，包括提供具有用于在其上形成介电绝缘层的工艺表面的半导体晶片; 沉积介电绝缘层; 并且使包含暴露表面的介电绝缘层经受包括干法等离子处理和湿法中的至少一种的亲水性增加处理，包括使暴露表面与包含表面活性剂的亲水性增加溶液接触，然后进行烘烤处理 以改善相邻沉积材料层的粘附性。

公开(公告)号：US06770570B2

公开(公告)日：2004-08-03

申请号：US10295609

申请日：2002-11-15

申请人： Lih-Ping Li ,  Hsin-Hsien Lu ,  Syun-Ming Jang

发明人： Lih-Ping Li ,  Hsin-Hsien Lu ,  Syun-Ming Jang

IPC分类号： H01L21469

CPC分类号： H01L21/76828 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835

摘要： A semiconductor device 100 includes a low-k dielectric insulator 104. In the preferred embodiment, a low-k dielectric material 104 is deposited. This material 104 is then cured using a plasma cure step. The cure process causes the density of the top portion 106 of layer 104 to be increased. The higher density portion 106, however, also has a higher dielectric constant. As a result, the dielectric constant of the layer 104 can be reduced by removing this higher density portion 106. This leads to a lower dielectric constant (e.g., less than about 3) of the bulk film.

摘要翻译： 半导体器件100包括低k电介质绝缘体104.在优选实施例中，沉积低k电介质材料104。 然后使用等离子体固化步骤固化该材料104。 固化过程使得层104的顶部106的密度增加。 然而，较高密度部分106也具有较高的介电常数。 结果，可以通过去除该较高密度部分106来降低层104的介电常数。这导致本体膜的较低的介电常数（例如小于约3）。

公开(公告)号：US20060270237A1

公开(公告)日：2006-11-30

申请号：US11497588

申请日：2006-08-02

申请人： Chia-Che Chuang ,  Wen-Chih Chiou ,  Hsin-Hsien Lu ,  Liang-Guang Chen

发明人： Chia-Che Chuang ,  Wen-Chih Chiou ,  Hsin-Hsien Lu ,  Liang-Guang Chen

IPC分类号： H01L21/461 ,  B24B7/00

CPC分类号： B24B53/017 ,  B24B37/042 ,  B24B49/16

摘要： An apparatus and method suitable for the pre-conditioning of a polishing pad on a CMP apparatus prior to the polishing of production wafers on the apparatus. The apparatus includes a pre-conditioning arm on which is mounted an ingot of suitable material. In use, the ingot is pressed against the polishing surface of the rotating polishing pad for a selected period of time to increase the temperature of the polishing surface by friction. The pre-conditioned polishing pad facilitates uniform polishing rates of production semiconductor wafers subsequently polished on the apparatus.

摘要翻译： 一种适于在抛光装置上的生产晶片之前对CMP装置上的抛光垫进行预处理的装置和方法。 该装置包括预调节臂，在其上安装合适材料的锭。 在使用中，将铸锭压在旋转的抛光垫的抛光表面上一段选定的时间，以通过摩擦来增加抛光表面的温度。 预处理的抛光垫有助于随后在设备上抛光的生产半导体晶片的均匀抛光速率。

公开(公告)号：US08252682B2

公开(公告)日：2012-08-28

申请号：US12704695

申请日：2010-02-12

申请人： Ku-Feng Yang ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

发明人： Ku-Feng Yang ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L2224/02372

摘要： A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer. One or more electrical contacts are formed in the dielectric layer for electrical connection to the exposed one or more TSVs.

摘要翻译： 提供了一种用于薄化晶片的方法。 在一个实施例中，提供具有多个半导体芯片的晶片，晶片具有第一侧和与第一侧相对的第二侧，其中每个芯片包括一组穿通硅通孔（TSV），每个TSV 基本上被衬垫层和阻挡层密封。 提供晶片载体以附接到晶片的第二侧。 晶片的第一侧变薄并且凹陷以部分地暴露衬里层，阻挡层和从晶片突出的TSV的部分。 隔离层沉积在晶片的第一侧和衬垫层，阻挡层和TSV的顶部之上。 此后，绝缘层沉积在隔离层上。 然后将绝缘层平坦化以暴露TSV的顶部。 电介质层沉积在晶片的平坦化第一侧上。 在电介质层中形成一个或多个电触头，用于与暴露的一个或多个TSV电连接。

公开(公告)号：US20080233839A1

公开(公告)日：2008-09-25

申请号：US11727119

申请日：2007-03-23

申请人： Hsin-Hsien Lu ,  Liang-Guang Chen ,  Tien-I Bao ,  Shau-Lin Shue

发明人： Hsin-Hsien Lu ,  Liang-Guang Chen ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： C25F3/30

CPC分类号： B24B37/22 ,  B24B37/042 ,  B24B37/24

摘要： Embodiments of a polisher for chemical mechanical planarization. The polisher includes a polishing pad structure containing a first reactant therein, and a second reactant in a polishing environment over the polishing pad structure. The first reactant and the second reactant react endothermically upon contact when polishing a wafer surface between the polishing pad structure and the polishing environment.

摘要翻译： 用于化学机械平面化的抛光机的实施例。 抛光机包括在其中包含第一反应物的抛光垫结构和在抛光环境中的抛光垫结构上的第二反应物。 当抛光抛光垫结构和抛光环境之间的晶片表面时，第一反应物和第二反应物在接触时发生吸热反应。

公开(公告)号：US08889544B2

公开(公告)日：2014-11-18

申请号：US13028889

申请日：2011-02-16

申请人： Yung-Hsu Wu ,  Hsin-Hsien Lu ,  Tien-I Bao ,  Shau-Lin Shue

发明人： Yung-Hsu Wu ,  Hsin-Hsien Lu ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L21/311 ,  H01L23/532 ,  H01L21/02 ,  H01L21/321

CPC分类号： H01L21/3212 ,  H01L21/02203 ,  H01L21/02348 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/7684 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： The disclosure provides mechanisms of performing metal chemical-mechanical polishing (CMP) without significant loss of copper and a dielectric film of damascene structures. The mechanisms use a metal CMP stop layer made of a low-k dielectric film with a porogen, which significantly reduces the removal rate of the metal CMP stop layer by metal CMP. The metal CMP stop layer is converted into a porous low-k dielectric film after a cure (or curing) to remove or convert the porogen. The low-k value, such as equal to or less than about 2.6, of the metal CMP stop layer makes the impact of using of the metal CMP stop layer on RC delay from minimum to none. Further the CMP stop layer protects the porous low-k dielectric film underneath from exposure to water, organic compounds, and mobile ions in the CMP slurry.

摘要翻译： 本公开提供了进行金属化学机械抛光（CMP）而不显着损失铜和镶嵌结构的介电膜的机理。 这些机制使用由具有致孔剂的低k电介质膜制成的金属CMP停止层，这显着地降低了通过金属CMP的金属CMP停止层的去除速率。 在固化（或固化）之后，将金属CMP停止层转化为多孔低k电介质膜以去除或转化致孔剂。 金属CMP停止层的低k值（例如等于或小于约2.6）使得金属CMP停止层的使用对RC延迟的影响从最小到无。 此外，CMP停止层保护下面的多孔低k电介质膜不暴露于CMP浆料中的水，有机化合物和移动离子。

公开(公告)号：US20110198721A1

公开(公告)日：2011-08-18

申请号：US12704695

申请日：2010-02-12

申请人： Ku-Feng YANG ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

发明人： Ku-Feng YANG ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

IPC分类号： H01L23/544 ,  H01L21/304 ,  H01L21/306 ,  H01L29/06 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L2224/02372

摘要： A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer. One or more electrical contacts are formed in the dielectric layer for electrical connection to the exposed one or more TSVs.

摘要翻译： 提供了一种用于薄化晶片的方法。 在一个实施例中，提供具有多个半导体芯片的晶片，晶片具有第一侧和与第一侧相对的第二侧，其中每个芯片包括一组穿通硅通孔（TSV），每个TSV 基本上被衬垫层和阻挡层密封。 提供晶片载体以附接到晶片的第二侧。 晶片的第一侧变薄并且凹陷以部分地暴露衬里层，阻挡层和从晶片突出的TSV的部分。 隔离层沉积在晶片的第一侧和衬垫层，阻挡层和TSV的顶部之上。 此后，绝缘层沉积在隔离层上。 然后将绝缘层平坦化以暴露TSV的顶部。 电介质层沉积在晶片的平坦化第一侧上。 在电介质层中形成一个或多个电触头，用于与暴露的一个或多个TSV电连接。