公开(公告)号：US20240022528A1

公开(公告)日：2024-01-18

申请号：US18357710

申请日：2023-07-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY

IPC: H04L49/90 ,  H04L49/109 ,  H04L69/22 ,  H04L67/568

CPC classification number: H04L49/9042 ,  H04L49/109 ,  H04L69/22 ,  H04L67/568

Abstract: In an example, a system includes a network port that receives a packet; a first memory; a second memory; and a packet analyzer coupled to the network port. The packet analyzer operates to divide the packet into multiple fragments, analyze each of the multiple fragments to determine whether the corresponding fragment has a first priority level or a second, lower, priority level, determine whether to store each of the multiple fragments in the first memory or the second memory based on the priority level determined for that fragment, store each fragment determined to have the first priority level in the first memory, and store each fragment determined to have the second priority level in the second memory. The network port, packet analyzer and the first memory, which may be a cache memory, may be embodied on a chip, and the second memory may be external to the chip.

公开(公告)号：US20230222072A1

公开(公告)日：2023-07-13

申请号：US18186524

申请日：2023-03-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Kishon Vijay Abraham ISRAEL VIJAYPONRAJ ,  Mihir Narendra MODY ,  Jason A.T. Jones

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4221 ,  G06F2213/0026

Abstract: A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root I/O virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.

公开(公告)号：US20230117485A1

公开(公告)日：2023-04-20

申请号：US18084635

申请日：2022-12-20

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra MODY ,  Niraj NANDAN ,  Rajasekhar Reddy ALLU

IPC: G06F3/06 ,  G06F13/28

Abstract: An integrated circuit includes: a local memory; and a first processing circuit coupled to the local memory. The first processing component is configured to: receive a first set of image data; perform a first image processing operation on the first set of image data to produce a second set of image data; and store at least some of the second set of image data into the local memory. The integrated circuit also includes a second processing circuit coupled to the local memory and configured to: receive at least some of the second set of image data from the local memory; and perform a second image processing operation on the second set of image data to produce a third set of image data.

公开(公告)号：US20230004855A1

公开(公告)日：2023-01-05

申请号：US17363856

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra MODY ,  Kumar DESAPPAN ,  Gregory Raymond SHURTZ ,  Jason A.T. JONES

IPC: G06N20/00 ,  G06F9/50

Abstract: Techniques for executing machine learning (ML) models including receiving an indication to execute an ML model on a processing core; determining a resource allocation for executing the ML model on the processing core; determining that a layer of the ML model will use a first amount of the resource, wherein the first amount is more than an amount of the resource allocated; determining that an adaptation may be applied to executing the layer of the ML model; executing the layer of the ML model using the adaptation, wherein executing the layer using the adaptation reduces the first amount of the resource used by the layer as compared to executing the layer without using the adaptation; and outputting a result of the ML model based on the executed layer.

公开(公告)号：US20220408064A1

公开(公告)日：2022-12-22

申请号：US17895191

申请日：2022-08-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shashank DABRAL ,  Mihir Narendra MODY ,  Denis BEAUDOIN ,  Niraj NANDAN ,  Gang HUA

IPC: H04N9/04 ,  G06T3/40 ,  G06T5/00

Abstract: A method of de-mosaicing pixel data from an image processor includes generating a pixel block that includes a plurality of image pixels. The method also includes determining a first image gradient between a first set of pixels of the pixel block and a second image gradient between a second set of pixels of the pixel block. The method also includes determining a first adaptive threshold value based on intensity of a third set of pixels of the pixel block. The pixels of the third set of pixels are adjacent to one another. The method also includes filtering the pixel block in a vertical, horizontal, or neutral direction based on the first and second image gradients and the first adaptive threshold value utilizing a plurality of FIR filters to generate a plurality of component images.

公开(公告)号：US20220391219A1

公开(公告)日：2022-12-08

申请号：US17888533

申请日：2022-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Denis Roland BEAUDOIN ,  Gregory Raymond SHURTZ ,  Santhanakrishnan Badri NARAYANAN ,  Mark Adrian BRYANS ,  Mihir Narendra MODY ,  Jason A.T. JONES ,  Jayant THAKUR

IPC: G06F9/4401 ,  H04L45/00 ,  H04L47/32 ,  G06F13/28 ,  H04L49/351

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

公开(公告)号：US20220263979A1

公开(公告)日：2022-08-18

申请号：US17739291

申请日：2022-05-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gang HUA ,  Mihir Narendra MODY ,  Rajasekhar Reddy ALLU ,  Niraj NANDAN ,  Shashank DABRAL

IPC: H04N5/217 ,  H04N9/04 ,  H04N5/357

Abstract: In some examples, a method comprises receiving pixel data from an image capture device having a color filter, wherein the pixel data represents a portion of an image. The method further includes performing wavelet decomposition on the pixel data to produce decomposed pixel data and determining a local intensity of the pixel data. The method also includes determining a noise threshold value based on the local intensity and a noise intensity function that is based on the color filter; determining a noise value for the pixel data based on the decomposed pixel data and the noise threshold value; and correcting the pixel data based on the noise value to produce an output image.

公开(公告)号：US20210326050A1

公开(公告)日：2021-10-21

申请号：US17233361

申请日：2021-04-16

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra MODY ,  Niraj NANDAN ,  Rajasekhar Reddy ALLU

IPC: G06F3/06 ,  G06F13/28

Abstract: An integrated circuit includes: a local memory; and a first processing circuit coupled to the local memory. The first processing component is configured to: receive a first set of image data; perform a first image processing operation on the first set of image data to produce a second set of image data; and store at least some of the second set of image data into the local memory. The integrated circuit also includes a second processing circuit coupled to the local memory and configured to: receive at least some of the second set of image data from the local memory; and perform a second image processing operation on the second set of image data to produce a third set of image data.

公开(公告)号：US20210232515A1

公开(公告)日：2021-07-29

申请号：US17134861

申请日：2020-12-28

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan GOVINDARAJAN ,  Kishon Vijay Abraham ISRAEL VIJAYPONRAJ ,  Mihir Narendra MODY

IPC: G06F13/20 ,  G06F13/42

Abstract: A configurable multi-function Peripheral Component Interchange Express (PCIe) endpoint controller, integrated in a system-on-chip (SoC), that exposes multiple functions of multiple processing subsystems (e.g., peripherals) to a host. The SoC may include a centralized transaction tunneling unit and a multi-function interrupt manager. The processing subsystems output data to the host via the centralized transaction tunneling unit, which translates addresses provided by the host to a local address of the SoC. Therefore, the centralized transaction tunneling unit enables those processing subsystems to consume addresses provided by the host without the need for software intervention and software-based translation. The SoC may also provide isolation between each function provided by the processing systems. The multi-function interrupt manager enables the endpoint controller to propagate interrupt messages received from the processing subsystems to the host.

公开(公告)号：US20210203622A1

公开(公告)日：2021-07-01

申请号：US17122215

申请日：2020-12-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY

IPC: H04L12/861 ,  H04L29/06 ,  H04L29/08 ,  H04L12/933

Abstract: In some examples, a system on chip (SOC) comprises a network switch configured to receive a packet and to identify a flow identifier (ID) corresponding to a header of the packet. The SOC comprises a direct memory access (DMA) controller coupled to the network switch, where the DMA controller is configured to divide the packet into first and second fragments based on the flow ID and to assign a first hardware queue to the first fragment and a second hardware queue to the second fragment, and wherein the DMA controller is further configured to assign memory regions to the first and second fragments based on the first and second hardware queues. The SOC comprises a snoopy cache configured to store the first fragment to the snoopy cache or to memory based on a first cache allocation command, where the first cache allocation command is based on the memory region assigned to the first fragment, where the snoopy cache is further configured to store the second fragment to the snoopy cache or to memory based on a second cache allocation command, and where the second cache allocation command is based on the memory region assigned to the second fragment.