公开(公告)号：US11251088B2

公开(公告)日：2022-02-15

申请号：US16901815

申请日：2020-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49

Abstract: A semiconductor device includes an active area having source and drain regions and a channel region between the source and drain regions, an isolation structure surrounding the active area, and a gate structure over the channel region of the active area and over the isolation structure, wherein the isolation structure has a first portion under the gate structure and a second portion free from coverage by the gate structure, and a top of the first portion of the isolation structure is lower than a top of the second portion of the isolation structure.

公开(公告)号：US11152462B2

公开(公告)日：2021-10-19

申请号：US16525346

申请日：2019-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cong-Min Fang ,  Kang-Min Kuo ,  Shi-Min Wu

IPC: H01L29/06 ,  H01L21/762

Abstract: A semiconductor device includes a semiconductive substrate, a first semiconductive fin and a second semiconductive fin extending upwards from the semiconductive substrate, an isolation structure at least partially between the first semiconductive fin and the second semiconductive fin, a first semiconductive raised portion and a second semiconductive raised portion. The first semiconductive raised portion extends upwards from the semiconductive substrate, is buried under the isolation structure, and is between the first semiconductive fin and the second semiconductive fin. A top surface of the first semiconductive fin is higher than a top surface of the first semiconductive raised portion. The second semiconductive raised portion extends upwards from the semiconductive substrate, is buried under the isolation structure, and is between the first semiconductive raised portion and the second semiconductive fin.

公开(公告)号：US10439022B2

公开(公告)日：2019-10-08

申请号：US15830979

申请日：2017-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US10157810B2

公开(公告)日：2018-12-18

申请号：US15714099

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H01L29/40 ,  H01L29/41 ,  H01L23/29 ,  H01L23/532

Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

公开(公告)号：US20180350814A1

公开(公告)日：2018-12-06

申请号：US16057838

申请日：2018-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Chi Tsai ,  Kang-Min Kuo

IPC: H01L27/092

CPC classification number: H01L27/0924 ,  H01L21/265 ,  H01L21/266 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/66545 ,  H01L29/7843

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a metal-oxide-semiconductor (MOS) transistor, and a dielectric layer. The MOS transistor includes a gate structure formed over the substrate. The dielectric layer is formed aside the gate structure, and the dielectric layer is doped with a strain modulator. An effective lattice constant of the dielectric layer doped with the strain modulator is different from an original lattice constant of the dielectric layer prior to be doped with the strain modulator, wherein the strain modulator at least comprises silicon.

公开(公告)号：US10096596B2

公开(公告)日：2018-10-09

申请号：US14970036

申请日：2015-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cong-Min Fang ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/3213 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/02 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first source region, a second source region, a first drain region, and a second drain region. The semiconductor device structure includes a first gate structure over the substrate and between the first source region and the first drain region. The semiconductor device structure includes a second gate structure over the substrate and between the second source region and the second drain region. A first thickness of the first gate structure is greater than a second thickness of the second gate structure. A first gate width of the first gate structure is less than a second gate width of the second gate structure.

公开(公告)号：US10062695B2

公开(公告)日：2018-08-28

申请号：US14961900

申请日：2015-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Chi Tsai ,  Kang-Min Kuo

IPC: H01L21/331 ,  H01L27/092 ,  H01L21/266 ,  H01L21/3115 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/265 ,  H01L21/266 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/66545 ,  H01L29/7843

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a metal-oxide-semiconductor (MOS) transistor, and a dielectric layer. The MOS transistor includes a gate structure formed over the substrate. The dielectric layer is formed aside the gate structure, and the dielectric layer is doped with a strain modulator. An effective lattice constant of the dielectric layer modified by the doping with the strain modulator is different from an effective lattice constant of the dielectric layer prior to the doping.

公开(公告)号：US20180226297A1

公开(公告)日：2018-08-09

申请号：US15943671

申请日：2018-04-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L21/823456 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0607 ,  H01L29/49 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66621

Abstract: A semiconductor device includes a substrate, an isolation structure, and a gate structure. The substrate has an active area. The isolation structure surrounds the active area of the substrate. The gate structure is across the active area of the substrate. The isolation structure has a first portion under the gate structure and a second portion adjacent to the gate structure. A top surface of the first portion of the isolation structure is lower than a top surface of the second portion of the isolation structure.

公开(公告)号：US10014251B2

公开(公告)日：2018-07-03

申请号：US15062063

申请日：2016-03-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Chung Lai ,  Kang-Min Kuo ,  Yen-Ming Peng ,  Gwo-Chyuan Kuoh ,  Han-Wei Yang ,  Yi-Ruei Lin ,  Chin-Chia Chang ,  Ying-Chieh Liao ,  Che-Chia Hsu ,  Bor-Zen Tien

IPC: H01L23/525 ,  H01L21/306 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/06 ,  H01L29/167 ,  H01L21/56 ,  H01L23/31 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5256 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/306 ,  H01L21/32136 ,  H01L21/563 ,  H01L21/76202 ,  H01L21/76224 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device with the metal fuse is provided. The metal fuse connects an electronic component (e.g., a transistor) and a existing dummy feature which is grounded. The protection of the metal fuse can be designed to start at the beginning of the metallization formation processes. The grounded dummy feature provides a path for the plasma charging to the ground during the entire back end of the line process. The metal fuse is a process level protection as opposed to the diode, which is a circuit level protection. As a process level protection, the metal fuse protects subsequently-formed circuitry. In addition, no additional active area is required for the metal fuse in the chip other than internal dummy patterns that are already implemented.

公开(公告)号：US09911821B2

公开(公告)日：2018-03-06

申请号：US14940832

申请日：2015-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ruei Yeh ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/768 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L29/518 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a metal gate electrode structure over the semiconductor substrate. The semiconductor device structure includes an insulating layer over the semiconductor substrate and surrounding the metal gate electrode structure. The semiconductor device structure includes a first metal nitride layer over a first top surface of the metal gate electrode structure and in direct contact with the metal gate electrode structure. The first metal nitride layer includes a nitride material of the metal gate electrode structure.