公开(公告)号：US12069965B2

公开(公告)日：2024-08-20

申请号：US18353569

申请日：2023-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Ya-Jui Tsou ,  Zong-You Luo ,  Chee-Wee Liu ,  Shao-Yu Lin ,  Liang-Chor Chung ,  Chih-Lin Wang

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01

Abstract: A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.

公开(公告)号：US11778923B2

公开(公告)日：2023-10-03

申请号：US17525927

申请日：2021-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Ya-Jui Tsou ,  Zong-You Luo ,  Chee-Wee Liu ,  Shao-Yu Lin ,  Liang-Chor Chung ,  Chih-Lin Wang

IPC: H01L43/10 ,  H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01

Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer, a spacer layer over the pinned layer, a reference layer over the spacer layer, and a tunnel barrier layer over the reference layer. The SOT layer has a top surface substantially coplanar with a top surface of the tunnel barrier layer of the memory stack. The free layer interconnects the SOT layer and the tunnel barrier layer.

公开(公告)号：US11728376B2

公开(公告)日：2023-08-15

申请号：US17445692

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L21/28264 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US10978389B2

公开(公告)日：2021-04-13

申请号：US16707953

申请日：2019-12-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Sheng Zheng ,  Chih-Lin Wang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528

Abstract: A device includes a first dielectric layer, a first conductor, a second dielectric layer, a second conductor, and an etch stop layer. The first conductor is in the first dielectric layer. The second dielectric layer is over the first dielectric layer. The second conductor is in the second dielectric layer and electrically connected to the first conductor. The second conductor has a first portion over a top surface of the first conductor and a second portion extending downwards from the first portion and around the first conductor. The etch stop layer has a first portion between the second portion of the second conductor and the first dielectric layer and a second portion between the first dielectric layer and the second dielectric layer. A top surface of the first portion of the etch stop layer is lower than a top surface of the second portion of the etch stop layer.

公开(公告)号：US10522543B2

公开(公告)日：2019-12-31

申请号：US16055526

申请日：2018-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo ,  Cheng-Wei Lian

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/40 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

Abstract: Methods for forming a semiconductor structure are provided. The method includes forming a first dummy gate structure and forming first spacers over a sidewall of the first dummy gate structure. The method includes removing the first dummy gate structure to form a first trench between the first spacers and forming a first capping layer in the first trench. A first portion of the first capping layer covers a sidewall of the first trench and a second portion of the first capping layer covers a bottom surface of the first trench. The method further includes oxidizing a sidewall of the first portion of the first capping layer and a top surface of the second portion of the first capping layer to form a first capping oxide layer and forming a first work function metal layer and forming a first gate electrode layer over the first work function metal layer.

公开(公告)号：US10475699B2

公开(公告)日：2019-11-12

申请号：US15888999

申请日：2018-02-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jia Hsieh ,  Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/768 ,  H01L29/16 ,  H01L29/161 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78 ,  H01L23/485 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/165 ,  H01L23/532

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

公开(公告)号：US09887129B2

公开(公告)日：2018-02-06

申请号：US14477689

申请日：2014-09-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jia Hsieh ,  Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/94 ,  H01L21/768 ,  H01L29/16 ,  H01L29/161 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78 ,  H01L23/485 ,  H01L21/8238 ,  H01L21/311 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/31105 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76855 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

公开(公告)号：US09331178B2

公开(公告)日：2016-05-03

申请号：US14819654

申请日：2015-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Chih Lin ,  Long-Jie Hong ,  Chih-Lin Wang ,  Chia-Der Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L29/06 ,  H01L21/3105

CPC classification number: H01L29/66795 ,  H01L21/31055 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底中形成两个隔离结构以在衬底中的两个隔离结构之间限定翅片结构。 形成虚拟栅极和间隔物，桥接两个隔离结构和鳍状结构。 用虚拟栅极和间隔物作为掩模蚀刻两个隔离结构，以在两个隔离结构中的间隔物下方形成多个斜面。 在多个斜面上形成栅极蚀刻停止层。 去除虚拟栅极和虚拟栅极之下的两个隔离结构以产生由间隔物和栅极蚀刻停止层限制的空腔。 然后在空腔中形成栅极。

公开(公告)号：US12148792B2

公开(公告)日：2024-11-19

申请号：US18358399

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US11749328B2

公开(公告)日：2023-09-05

申请号：US17871983

申请日：2022-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Zong-You Luo ,  Ya-Jui Tsou ,  Chee-Wee Liu ,  Shao-Yu Lin ,  Liang-Chor Chung ,  Chih-Lin Wang

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10B61/20 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.