公开(公告)号：US11038059B2

公开(公告)日：2021-06-15

申请号：US16515020

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Sheng Liang ,  Kuo-Hua Pan ,  Hsin-Che Chiang ,  Ming-Heng Tsai

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417

Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.

公开(公告)号：US20200335337A1

公开(公告)日：2020-10-22

申请号：US16916116

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L21/033 ,  H01L29/423 ,  H01L21/311 ,  H01L21/764

Abstract: A semiconductor device includes a gate electrode, spacers and a hard mask structure. The spacers are disposed on opposite sidewalls of the gate electrode. The hard mask structure includes a first hard mask layer and a second hard mask layer. A lower portion of the first hard mask layer is disposed between the spacers and on the gate electrode, and a top portion of the first hard mask layer is surrounded by the second hard mask layer.

公开(公告)号：US20200243396A1

公开(公告)日：2020-07-30

申请号：US16853474

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Buo-Chin Hsu ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L29/06 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

公开(公告)号：US10714342B2

公开(公告)日：2020-07-14

申请号：US16164779

申请日：2018-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC: H01L21/033 ,  H01L29/423 ,  H01L21/311 ,  H01L21/764

Abstract: Semiconductor devices and method of forming the same are disclosed. One of the semiconductor devices includes a substrate, a gate structure, a plug and a hard mask structure. The gate structure is disposed over the substrate. The plug is disposed over and electrically connected to the gate structure. The hard mask structure is disposed over the gate structure and includes a first hard mask layer and a second hard mask layer. The first hard mask layer surrounds and is in contact with the plug. The second hard mask layer surrounds the first hard mask layer and has a bottom surface at a height between a top surface and a bottom surface of the first hard mask layer. A material of the first hard mask layer is different from a material of the second hard mask layer.

公开(公告)号：US20200044074A1

公开(公告)日：2020-02-06

申请号：US16515020

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Sheng Liang ,  Kuo-Hua Pan ,  Hsin-Che Chiang ,  Ming-Heng Tsai

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.

公开(公告)号：US10553481B2

公开(公告)日：2020-02-04

申请号：US15692212

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jen Chang ,  Min-Yann Hsieh ,  Hua Feng Chen ,  Kuo-Hua Pan

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

公开(公告)号：US20190333822A1

公开(公告)日：2019-10-31

申请号：US15964177

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Buo-Chin Hsu ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311

Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

公开(公告)号：US10332786B2

公开(公告)日：2019-06-25

申请号：US15619595

申请日：2017-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Che Tsai ,  Min-Yann Hsieh ,  Hua-Feng Chen ,  Kuo-Hua Pan

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/283

Abstract: A method for manufacturing a semiconductor device includes forming a gate stack over a substrate; forming an interlayer dielectric over the substrate to cover the gate stack; forming an opening in the interlayer dielectric to expose to the gate stack; forming a glue layer over the interlayer dielectric and in the opening; partially removing the glue layer, in which a portion of the glue layer remain in the opening; and tuning a profile of the remained portion of the glue layer.

公开(公告)号：US20190067093A1

公开(公告)日：2019-02-28

申请号：US15692212

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jen Chang ,  Min-Yann Hsieh ,  Hua Feng Chen ,  Kuo-Hua Pan

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

公开(公告)号：US10134873B2

公开(公告)日：2018-11-20

申请号：US15355901

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Chun-Sheng Liang ,  Shu-Hui Wang ,  Kuo-Hua Pan

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/40 ,  H01L29/51

Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.