公开(公告)号：US20210050247A1

公开(公告)日：2021-02-18

申请号：US17085245

申请日：2020-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Chi-Kang Liu ,  Chi-Wen Liu

IPC: H01L21/762 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/266 ,  H01L21/306 ,  H01L21/324

Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.

公开(公告)号：US10854724B2

公开(公告)日：2020-12-01

申请号：US16195591

申请日：2018-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd. ,  National Taiwan University

Inventor： Che-Wei Yang ,  Chi-Wen Liu ,  Hao-Hsiung Lin ,  Ling-Yen Yeh

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L21/02 ,  H01L29/78 ,  H01L27/12 ,  H01L21/20

Abstract: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.

公开(公告)号：US20200343141A1

公开(公告)日：2020-10-29

申请号：US16928585

申请日：2020-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Sheng Li ,  Hsin-Chieh Huang ,  Chi-Wen Liu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/311

Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.

公开(公告)号：US10340383B2

公开(公告)日：2019-07-02

申请号：US15277079

申请日：2016-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Huang-Siang Lan ,  CheeWee Liu ,  Chi-Wen Liu ,  Shih-Hsien Huang ,  I-Hsieh Wong ,  Hung-Yu Yeh ,  Chung-En Tsai

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm−3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.

公开(公告)号：US20190148523A1

公开(公告)日：2019-05-16

申请号：US16229026

申请日：2018-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ming Peng ,  Chi-Wen Liu ,  Hsin-Chieh Huang ,  Yi-Ju Hsu ,  Horng-Huei Tseng

IPC: H01L29/66 ,  H01L29/78

Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.

公开(公告)号：US10283590B2

公开(公告)日：2019-05-07

申请号：US15203674

申请日：2016-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ling-Yen Yeh ,  Yee-Chia Yeo ,  Chi-Wen Liu

IPC: H01L27/00 ,  H01L21/00 ,  H01L29/10 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/778 ,  H01L29/423 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78

Abstract: Exemplary FET devices having 2D material layer active regions and methods of fabricating thereof are described. For example, a black phosphorus active region has a first thickness in the channel region and a second, greater, thickness in the source/drain (S/D) region. The BP in the S/D region has a sidewall that interfaces a contact disposed over the FET. A gate electrode is disposed over the channel region. In some embodiments, the sidewall has passivated edge. In some embodiments, the sidewall is nonlinear. In some embodiments, the stress layer is disposed over the 2D material layer.

公开(公告)号：US20190123211A1

公开(公告)日：2019-04-25

申请号：US16224921

申请日：2018-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd. ,  National Taiwan University

Inventor： Shih-Yen Lin ,  Chi-Wen Liu ,  Chong-Rong Wu ,  Xiang-Rui Chang

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/66 ,  H01L21/02 ,  H01L29/778 ,  H01L29/417 ,  H01L29/267 ,  H01L29/16

Abstract: A semiconductor device includes a first film disposed over a semiconductor substrate, the first film comprising a first transition metal dichalcogenide; a second film disposed over the first film, the second film comprising a second transition metal dichalcogenide different from the first transition metal dichalcogenide; source and drain features formed over the second film; a first gate stack formed over the second film and interposed between the source and drain features; and a second gate stack formed over the semiconductor substrate opposite from the first gate stack such that the semiconductor substrate is between the first and second gate stacks.

公开(公告)号：US20190123184A1

公开(公告)日：2019-04-25

申请号：US16227931

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Cheng-Cheng Kuo ,  Chi-Wen Liu ,  Ming Zhu

IPC: H01L29/66 ,  H01L29/739 ,  H01L21/324 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/265 ,  H01L29/06 ,  H01L29/786

Abstract: Tunneling field-effect transistors (TFETs) and associated methods of fabrication are disclosed herein. An exemplary TFET includes a protrusion that extends vertically from a substrate. A drain region is in a bottommost portion of the protrusion. A source region is in a topmost portion of the protrusion. A gate stack that wraps a middle portion of the protrusion. The gate stack further wraps around a portion of the source region and a portion of the drain region. Spacers are along a portion of the topmost portion of the protrusion. The TFET further includes a drain contact coupled to the drain region, a gate contact coupled to the gate stack, and a source contact coupled to the source region. The source contact has a width that is greater than a width of the source region. The source contact is disposed on the source region and a portion of the spacers.

公开(公告)号：US10164076B2

公开(公告)日：2018-12-25

申请号：US15392579

申请日：2016-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Cheng-Cheng Kuo ,  Chi-Wen Liu ,  Ming Zhu

IPC: H01L29/66 ,  H01L21/336 ,  H01L21/332 ,  H01L21/8238 ,  H01L29/739 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/324 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method for forming a tunneling field-effect transistor (TFET) is disclosed. The method includes etching a semiconductor substrate to form a semiconductor protrusion that protrudes out from a top surface of the semiconductor substrate, forming a drain region in lower portion of the semiconductor protrusion, and patterning a gate stack layer to form a gate stack. The gate stack has a gating surface that directly contacts and wraps around a middle portion of the semiconductor protrusion. The method further includes forming a source region in an upper portion of the semiconductor protrusion and forming a source contact over the source region, the source contact have a first width that is larger than a width of the source region.

公开(公告)号：US10032873B2

公开(公告)日：2018-07-24

申请号：US15164824

申请日：2016-05-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ming Chang ,  Chi-Wen Liu ,  Cheng-Chien Li ,  Hsin-Chieh Huang

IPC: H01L29/786 ,  H01L29/36 ,  H01L29/167 ,  H01L29/06 ,  H01L29/78 ,  H01L21/265 ,  H01L21/02 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.