Methods of treating aneurysm
    52.
    发明授权
    Methods of treating aneurysm 有权
    治疗动脉瘤的方法

    公开(公告)号:US08748410B2

    公开(公告)日:2014-06-10

    申请号:US13229093

    申请日:2011-09-09

    摘要: The present invention is directed to a method for treating aneurysms in vascular tissue. The method includes administering a bisphosphonate compound to a subject in an amount which is effective against the formation or progression of aneurysm, or which is effective to induce regression of an established aneurysm. In alternative methods, an anti-RANKL neutralizing antibody is administered to the subject to achieve analogous anti-aneurysm effect. The methods of particular advantage in the treatment of subjects having an abdominal aortic aneurysm, a relatively common, and life-threatening, condition.

    摘要翻译: 本发明涉及治疗血管组织中的动脉瘤的方法。 所述方法包括以对动脉瘤形成或进展有效的量给予受试者双膦酸盐化合物,或有效诱导建立的动脉瘤消退的量。 在替代方法中,向受试者施用抗RANKL中和抗体以获得类似的抗动脉瘤效应。 治疗具有腹主动脉瘤的受试者,相对常见的和危及生命的病症中特别有利的方法。

    ANALYTE DETECTION METHOD
    53.
    发明申请
    ANALYTE DETECTION METHOD 有权
    分析检测方法

    公开(公告)号:US20130302781A1

    公开(公告)日:2013-11-14

    申请号:US13878815

    申请日:2011-10-11

    IPC分类号: G01N33/94

    摘要: Disclosed is a method of determining the presence of an analyte of interest by means of a detection of a reaction product between the analyte of interest and a reactant, the method comprising extracting the analyte of interest from a complex sample matrix; transferring the analyte of interest to an initial reaction mixture; performing a background measurement on the initial reaction mixture comprising at most a negligible concentration of the reaction product, wherein the reaction conditions present in said initial reaction mixture at least reduce the reaction rate of the formation of the reaction product such that the background measurement can be performed without a measurable change in said negligible concentration; altering the reaction conditions in the initial reaction mixture to accelerate said reaction rate; continuing said reaction until the concentration of the reaction product has stabilized; performing a second measurement on the resultant reaction mixture to obtain a signal correlated to said concentration; and determining the presence of the analyte of interest from a difference between the background measurement and the second measurement. In a preferred embodiment, the analyte of interest is Propofol (2,6-di-isopropylphenol), and the reactant is the activated Gibbs reagent (2,6-dichloroquinoneimine).

    摘要翻译: 公开了通过检测目标分析物和反应物之间的反应产物来确定感兴趣分析物的存在的方法,该方法包括从复杂样品基质提取目的分析物; 将目标分析物转移到初始反应混合物中; 对最初反应混合物进行背景测量,该反应混合物至少含有可忽略的反应产物浓度,其中存在于所述初始反应混合物中的反应条件至少降低反应产物形成的反应速率,使得背景测量可以 在所述可忽略的浓度中没有可测量的变化; 改变初始反应混合物中的反应条件以加速所述反应速率; 继续反应直到反应产物的浓度稳定; 对所得反应混合物进行第二次测定以获得与所述浓度相关的信号; 以及从背景测量和第二测量之间的差异确定感兴趣分析物的存在。 在优选的实施方案中,感兴趣的分析物是异丙酚(2,6-二异丙基苯酚),反应物是活化的吉布斯试剂(2,6-二氯喹啉亚胺)。

    PHASE CHANGE MEMORY CELL AND FABRICATION METHOD THEREOF
    54.
    发明申请
    PHASE CHANGE MEMORY CELL AND FABRICATION METHOD THEREOF 审中-公开
    相变存储单元及其制造方法

    公开(公告)号:US20130292629A1

    公开(公告)日:2013-11-07

    申请号:US13202697

    申请日:2011-06-23

    IPC分类号: H01L45/00

    摘要: The present invention provides a phase change memory cell and fabrication method thereof, wherein said phase change memory cell comprises a semiconductor substrate, a first electrode layer, a phase change material layer, a second electrode layer and an extraction electrode, as well as a high resistance material layer used to prevent said phase change material layer from over-corrosion during the chemical mechanical polishing process, and wherein said high resistance material layer has a resistance ten or more times that of the phase change material layer and can be used to prevent phase change material layer from over-corrosion during the chemical mechanical polishing process and thus enhance the memory performance and the yield of phase change memory cell.

    摘要翻译: 本发明提供一种相变存储单元及其制造方法,其中所述相变存储单元包括半导体衬底,第一电极层,相变材料层,第二电极层和引出电极以及高 用于防止所述相变材料层在化学机械抛光工艺期间过度腐蚀的电阻材料层,并且其中所述高电阻材料层具有相变材料层的电阻的十倍或更多倍,并且可用于防止相位 在化学机械抛光过程中改变材料层的过度腐蚀,从而提高相变存储单元的记忆性能和产量。

    Method for acquiring graphics device interface invocation by using filter driver
    55.
    发明授权
    Method for acquiring graphics device interface invocation by using filter driver 有权
    使用过滤器驱动程序获取图形设备接口调用的方法

    公开(公告)号:US08395628B2

    公开(公告)日:2013-03-12

    申请号:US11776780

    申请日:2007-07-12

    摘要: A method for intercepting graphics device interface invocations by using filter driver which is transparent to graphics device interface engine and real display driver is disclosed. The method comprises steps of duplicating DDI function table returned from said real display driver, modifying DDI functions of said real display driver required for capturing screen update, creating auxiliary buffer area as updating buffer area for said screen update, and further processing said updating buffer area. With the method of the present invention, the support to video and 3D acceleration in the local computer can be realized by means of software, and the user can be provided with high-quality picture and display effect. Compared with the Mirror system in the prior art, since the present invention doesn't employ the Mirror system, the graphics device interface engine of the inventive system are not aware of the existence of the filter driver, the video and 3D acceleration function of the graphic card still remains. As a result, the function can be supported in the system, and applications employing video and 3D acceleration can be executed normally.

    摘要翻译: 公开了一种通过使用对图形设备接口引擎和实际显示驱动程序是透明的过滤器驱动程序拦截图形设备接口调用的方法。 该方法包括以下步骤:复制从所述实际显示驱动器返回的DDI功能表,修改捕获屏幕更新所需的所述真实显示驱动器的DDI功能,创建辅助缓冲区作为用于所述屏幕更新的更新缓冲区,以及进一步处理所述更新缓冲区 。 利用本发明的方法,可以通过软件实现对本地计算机中的视频和3D加速的支持,并且可以为用户提供高质量的图片和显示效果。 与现有技术中的Mirror系统相比,由于本发明不使用Mirror系统,本发明系统的图形设备接口引擎不知道是否存在过滤驱动器,视频和3D加速功能 图形卡仍然存在。 因此,该功能可以在系统中得到支持,采用视频和3D加速的应用程序可以正常执行。

    V-shaped resonators for addition of broad-area laser diode arrays
    56.
    发明授权
    V-shaped resonators for addition of broad-area laser diode arrays 有权
    用于添加广域激光二极管阵列的V形谐振器

    公开(公告)号:US08340151B2

    公开(公告)日:2012-12-25

    申请号:US12966423

    申请日:2010-12-13

    IPC分类号: H01S3/08

    CPC分类号: G02B27/14

    摘要: A system and method for addition of broad-area semiconductor laser diode arrays are described. The system can include an array of laser diodes, a V-shaped external cavity, and grating systems to provide feedback for phase-locking of the laser diode array. A V-shaped mirror used to couple the laser diode emissions along two optical paths can be a V-shaped prism mirror, a V-shaped stepped mirror or include multiple V-shaped micro-mirrors. The V-shaped external cavity can be a ring cavity. The system can include an external injection laser to further improve coherence and phase-locking.

    摘要翻译: 描述了用于添加广域半导体激光二极管阵列的系统和方法。 该系统可以包括激光二极管阵列,V形外腔和光栅系统,为激光二极管阵列的相位锁定提供反馈。 用于将激光二极管发射沿着两个光学路径耦合的V形镜可以是V形棱镜,V形阶梯镜或者包括多个V形微镜。 V形外腔可以是环形腔。 该系统可以包括外部注入激光器,以进一步提高相干性和相位锁定。

    Bit Scan Circuits and Method in Non-volatile Memory
    57.
    发明申请
    Bit Scan Circuits and Method in Non-volatile Memory 有权
    位扫描电路和非易失性存储器中的方法

    公开(公告)号:US20120321032A1

    公开(公告)日:2012-12-20

    申请号:US13164618

    申请日:2011-06-20

    IPC分类号: H03K23/40

    CPC分类号: G11C29/40 G11C29/44

    摘要: A circuit for counting in an N-bit string a number of bits M, having a first binary value includes N latch circuits in a daisy chain where each latch circuit has a tag bit that controls each to be either in a no-pass or pass state. Initially the tag bits are set according to the bits of the N-bit string where the first binary value corresponds to a no-pass state. A clock signal having a pulse train is run through the daisy chain to “interrogate” any no-pass latch circuits. It races right through any pass latch circuit. However, for a no-pass latch circuit, a leading pulse while being blocked also resets after a pulse period the tag bit from “no-pass” to “pass” state to allow subsequent pulses to pass. After all no-pass latch circuits have been reset, M is given by the number of missing pulses from the pulse train.

    摘要翻译: 用于以N位串计数具有第一二进制值的位数M的电路包括菊花链中的N个锁存电路,其中每个锁存电路具有控制每个锁存电路处于非通过或通过状态的标签位 州。 最初,标签位根据N位串的位进行设置,其中第一个二进制值对应于无通状态。 具有脉冲串的时钟信号通过菊花链行进,以询问任何无通路锁存电路。 它可以通过任何通过锁存电路进行比赛。 然而,对于无通路锁存电路,被阻塞的前导脉冲也在标签位从不通过到通过状态的脉冲周期之后复位,以允许随后的脉冲通过。 在所有无通路锁存电路复位之后,M由脉冲序列的丢失脉冲数给出。

    Structure and method for shuffling data within non-volatile memory devices
    60.
    发明授权
    Structure and method for shuffling data within non-volatile memory devices 有权
    在非易失性存储器件内混洗数据的结构和方法

    公开(公告)号:US08102705B2

    公开(公告)日:2012-01-24

    申请号:US12635449

    申请日:2009-12-10

    IPC分类号: G11C16/04 G11C7/10

    摘要: Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

    摘要翻译: 描述用于在多状态非易失性存储器中读取和写入数据的技术。 数据以二进制格式写入存储器,读入存储器中的数据寄存器,并在寄存器内“折叠”,然后以多状态格式写入存储器。 在折叠操作中,来自单个字线的二进制数据被折叠为多状态格式,并且当以多状态形式重写时,被写入另一个字线的仅一部分。 还描述了数据“展开”的相应的读取技术。 这些技术还允许在控制器上用纠错码(ECC)对数据进行编码,该错误校正码在将数据传送到存储器以二进制形式写入之前考虑其最终的多状态存储。 还提出了允许这种“折叠”操作的寄存器结构。 一组实施例包括本地内部数据总线,其允许在不同读/写堆栈的寄存器之间的数据,其中内部总线可以在内部数据折叠处理中使用。