公开(公告)号：US08664032B2

公开(公告)日：2014-03-04

申请号：US13101833

申请日：2011-05-05

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L31/18

CPC分类号： H01L27/14812 ,  H01L27/14837 ,  H01L31/035281 ,  H01L31/03529 ,  Y02E10/50

摘要： It is an object to provide a CCD solid-state image sensor, in which an area of a read channel is reduced and a rate of a surface area of a light receiving portion (photodiode) to an area of one pixel is increased. There is provided a solid-state image sensor, including: a first conductive type semiconductor layer; a first conductive type pillar-shaped semiconductor layer formed on the first conductive type semiconductor layer; a second conductive type photoelectric conversion region formed on the top of the first conductive type pillar-shaped semiconductor layer, an electric charge amount of the photoelectric conversion region being changed by light; and a high-concentrated impurity region of the first conductive type formed on a surface of the second conductive type photoelectric conversion region, the impurity region being spaced apart from a top end of the first conductive type pillar-shaped semiconductor layer by a predetermined distance, wherein a transfer electrode is formed on the side of the first conductive type pillar-shaped semiconductor layer via a gate insulating film, a second conductive type CCD channel region is formed below the transfer electrode, and a read channel is formed in a region between the second conductive type photoelectric conversion region and the second conductive type CCD channel region.

摘要翻译： 本发明的目的是提供一种CCD固态图像传感器，其中读取通道的面积减小，并且光接收部分（光电二极管）到一个像素的区域的表面积的比率增加。 提供了一种固态图像传感器，包括：第一导电型半导体层; 形成在第一导电型半导体层上的第一导电型柱状半导体层; 第二导电型光电转换区，形成在第一导电型柱状半导体层的顶部，光电转换区域的电荷量由光改变; 以及形成在所述第二导电型光电转换区域的表面上的所述第一导电类型的高浓度杂质区域，所述杂质区域与所述第一导电型柱状半导体层的顶端隔开预定距离， 其中，在所述第一导电型柱状半导体层的侧面经由栅极绝缘膜形成有转印电极，在所述转印电极的下方形成第二导电型CCD沟道区，在所述第二导电型柱状半导体层之间的区域形成读取沟道 第二导电型光电转换区域和第二导电型CCD沟道区域。

公开(公告)号：US08642426B2

公开(公告)日：2014-02-04

申请号：US13534615

申请日：2012-06-27

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/8249 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L27/092 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78642

摘要： It is an object to allow an inverter to be made up using a single island-shaped semiconductor, so as to provide a semiconductor device comprising a highly-integrated SGT-based CMOS inverter circuit. The object is achieved by a semiconductor device which comprises an island-shaped semiconductor layer, a first gate dielectric film surrounding a periphery of the island-shaped semiconductor layer, a gate electrode surrounding a periphery of the first gate dielectric film, a second gate dielectric film surrounding a periphery of the gate electrode, a tubular semiconductor layer surrounding a periphery of the second gate dielectric film, a first first-conductive-type high-concentration semiconductor layer disposed on top of the island-shaped semiconductor layer, a second first-conductive-type high-concentration semiconductor layer disposed underneath the island-shaped semiconductor layer, a first second-conductive-type high-concentration semiconductor layer disposed on top of the tubular semiconductor layer, and a second second-conductive-type high-concentration semiconductor layer disposed underneath the tubular semiconductor layer.

摘要翻译： 本发明的目的是允许使用单个岛状半导体构成逆变器，以提供包括高度集成的基于SGT的CMOS反相器电路的半导体器件。 该目的通过一种半导体器件实现，该半导体器件包括岛状半导体层，围绕岛状半导体层的周围的第一栅极电介质膜，围绕第一栅极电介质膜周围的栅电极，第二栅极电介质 围绕所述栅电极的周围的薄膜，围绕所述第二栅极电介质膜的周围的管状半导体层，设置在所述岛状半导体层的顶部的第一第一导电型高浓度半导体层， 布置在岛状半导体层下方的导电型高浓度半导体层，设置在管状半导体层顶部的第一第二导电型高浓度半导体层和第二第二导电型高浓度半导体层 层设置在管状半导体层下方。

公开(公告)号：US08519475B2

公开(公告)日：2013-08-27

申请号：US13289742

申请日：2011-11-04

申请人： Fujio Masuoka ,  Hiroki Nakamura ,  Shintaro Arai ,  Tomohiko Kudo ,  Navab Singh ,  Kavitha Devi Buddharaju ,  Shen Nansheng ,  Rukmani Devi Sayanthan

发明人： Fujio Masuoka ,  Hiroki Nakamura ,  Shintaro Arai ,  Tomohiko Kudo ,  Navab Singh ,  Kavitha Devi Buddharaju ,  Shen Nansheng ,  Rukmani Devi Sayanthan

IPC分类号： H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66666 ,  H01L29/78642

摘要： A semiconductor device includes a first insulating film formed between a gate electrode and a first flat semiconductor layer, and a sidewall-shaped second insulating film formed to surround an upper sidewall of a first columnar silicon layer while contacting an upper surface of the gate electrode and to surround a sidewall of the gate electrode and the first insulating film. The semiconductor device further includes a metal-semiconductor compound formed on each of an upper surface of a first semiconductor layer of the second conductive type formed in the entirety or the upper portion of the first flat semiconductor layer, and an upper surface of the second semiconductor layer of the second conductive type formed in the upper portion of the first columnar semiconductor layer.

摘要翻译： 半导体器件包括形成在栅极电极和第一平坦半导体层之间的第一绝缘膜，以及侧壁形状的第二绝缘膜，其形成为围绕第一柱状硅层的上侧壁，同时接触栅电极的上表面和 以围绕栅电极和第一绝缘膜的侧壁。 半导体器件还包括形成在第一导电类型的第一半导体层的上表面上的第一半导体层的整体或上部形成的金属半导体化合物和第二半导体的上表面 形成在第一柱状半导体层的上部的第二导电类型的层。

公开(公告)号：US08382576B2

公开(公告)日：2013-02-26

申请号：US12944389

申请日：2010-11-11

申请人： Hiroki Nakamura

发明人： Hiroki Nakamura

IPC分类号： A63F9/24

CPC分类号： G07F17/3267 ,  G07F17/32 ,  G07F17/3209 ,  G07F17/3244 ,  G07F17/3262 ,  G07F17/3288

摘要： To provide a gaming machine and a control method therefor, having a new entertainment characteristics, a slot machine 10 of the present invention, when a “BONUS” symbol 250 associated with a pick-up bonus game is selected, receives selection of any one of twenty little pig's noses 210 displayed. Then, a benefit associated with the selected little pig's nose 210 is awarded. When the benefit to be awarded is a “stick house” 218 which means “step-up”, a step-up occurs to the stick house stage and the expectation value for a payout is raised. Thus, when one little pig's nose 210 is selected out of the twenty little pig's noses 210 displayed in the stick house stage, the payout amount of the benefit associated with the little pig's nose 210 is increased.

摘要翻译： 为了提供具有新的娱乐特征的游戏机及其控制方法，本发明的老虎机10当选择与拾取奖励游戏相关联的奖励符号250时，接收二十个中的任一个的选择 显示猪的鼻子210。 然后，授予与所选小猪鼻子210相关的益处。 当被授予的利益是一个意味着升级的棍棒218时，棍棒屋阶段发生升压，提高了支付的期望值。 因此，当从出现在棒房阶段的二十只小猪的鼻子210中选出一只小猪的鼻子210时，与小猪鼻子210相关联的利益的支付量增加。

公开(公告)号：US08330089B2

公开(公告)日：2012-12-11

申请号：US12700294

申请日：2010-02-04

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L27/00 ,  H01L31/00

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14689

摘要： It is intended to provide a CMOS image sensor with a high degree of pixel integration. A solid-state imaging device comprises a signal line formed on a Si substrate, an island-shaped semiconductor formed on the signal line, and a pixel selection line. The island-shaped semiconductor includes: a first semiconductor layer connected to the signal line; a second semiconductor layer located above and adjacent to the first semiconductor layer; a gate connected to the second semiconductor layer through an insulating film; and a charge storage section comprised of a third semiconductor layer connected to the second semiconductor layer and adapted, in response to receiving light, to undergo a change in amount of electric charges therein; a fourth semiconductor layer located above and adjacent to the second and third semiconductor layers. The pixel selection line is connected to the fourth semiconductor layer formed as a top portion of the island-shaped semiconductor.

摘要翻译： 旨在提供具有高度像素集成度的CMOS图像传感器。 固态成像装置包括形成在Si衬底上的信号线，形成在信号线上的岛状半导体和像素选择线。 岛状半导体包括：连接到信号线的第一半导体层; 位于第一半导体层上方并与其相邻的第二半导体层; 通过绝缘膜与第二半导体层连接的栅极; 以及电荷存储部，包括连接到所述第二半导体层并且响应于接收光而适应于其中的电荷量的变化的第三半导体层; 位于第二和第三半导体层上方并与其相邻的第四半导体层。 像素选择线连接到形成为岛状半导体的顶部的第四半导体层。

公开(公告)号：US20120299068A1

公开(公告)日：2012-11-29

申请号：US13478359

申请日：2012-05-23

申请人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

发明人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

IPC分类号： H01L29/78

CPC分类号： H01L29/78642 ,  H01L29/42392 ,  H01L29/66772

摘要： It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 本发明的目的是提供一种能够获得用于降低栅极的电阻，期望的栅极长度，期望的源极和漏极配置以及柱状半导体的期望直径的结构的SGT制造方法。 该目的通过一种半导体器件制造方法来实现，该方法包括以下步骤：形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方形成第二导电型半导体层; 在柱状第一导电型半导体层周围形成栅极电介质膜和栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅极的顶部接触的侧壁状的电介质膜; 在所述浇口的侧壁上形成侧壁状的电介质膜; 以及在柱状第一导电型半导体层的上部和形成在柱状的第一导电型半导体层下方的第二导电型半导体层上形成第二导电型半导体层。

公开(公告)号：US20120142154A1

公开(公告)日：2012-06-07

申请号：US13354579

申请日：2012-01-20

申请人： FUJIO MASUOKA ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

发明人： FUJIO MASUOKA ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

IPC分类号： H01L21/336

CPC分类号： H01L29/78642 ,  H01L29/42392 ,  H01L29/66666

摘要： An SGT production method includes forming a pillar-shaped first-conductive-type semiconductor layer and forming a second-conductive-type semiconductor layer underneath the first-conductive-type semiconductor layer. A dummy gate dielectric film and a dummy gate electrode are formed around the first-conductive-type semiconductor layer and a first dielectric film is formed on an upper region of a sidewall of the first-conductive-type semiconductor layer in contact with a top of the gate electrode. A first dielectric film is formed on a sidewall of the gate electrode and a second-conductive-type semiconductor layer is formed in an upper portion of the first-conductive-type semiconductor layer. A second-conductive-type semiconductor layer is formed in an upper portion of the first-conductive-type semiconductor layer and a metal-semiconductor compound is formed on each of the second-conductive-type semiconductor layers. The dummy gate dielectric film and the dummy gate electrode are removed and a high-k gate dielectric film and a metal gate electrode are formed.

摘要翻译： SGT制造方法包括形成柱状的第一导电型半导体层，在第一导电型半导体层的下方形成第二导电型半导体层。 在第一导电型半导体层周围形成虚拟栅极电介质膜和虚拟栅电极，并且第一电介质膜形成在第一导电型半导体层的与顶部接触的第一导电型半导体层的侧壁的上部区域 栅电极。 第一电介质膜形成在栅电极的侧壁上，第二导电型半导体层形成在第一导电型半导体层的上部。 第二导电型半导体层形成在第一导电型半导体层的上部，并且在每个第二导电型半导体层上形成金属半导体化合物。 除去虚拟栅极电介质膜和虚拟栅电极，形成高k栅极电介质膜和金属栅电极。

公开(公告)号：US20110303966A1

公开(公告)日：2011-12-15

申请号：US13114681

申请日：2011-05-24

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/42328 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7889

摘要： A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped floating gate arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the floating gate and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the floating gate in such a manner that an inter-polysilicon insulating film is interposed between the control gate and the floating gate. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the upper, lower, and inner side surfaces of the control gate.

摘要翻译： 包括在非易失性半导体存储器中的非易失性半导体存储晶体管包括从基板侧依次形成的源极区，沟道区和漏极区的岛状半导体，中空柱状浮栅配置成 以沟道绝缘膜插入在浮动栅极和沟道区域之间的方式围绕沟道区域的外周，并且以这样的方式围绕浮动栅极的外周布置的中空柱状控制栅极 多晶硅间绝缘膜介于控制栅极和浮栅之间的方式。 多晶硅间绝缘膜被布置成位于控制栅极的浮动栅极和上，下和内侧表面之间。

公开(公告)号：US20110241122A1

公开(公告)日：2011-10-06

申请号：US13070028

申请日：2011-03-23

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： H01L27/11

CPC分类号： H01L27/11 ,  H01L21/823885

摘要： There is provided a high-integrated complementary metal-oxide semiconductor static random-access memory including an inverter. The inverter includes: a first pillar that is formed by integrating a first-conductivity-type semiconductor, a second-conductivity-type semiconductor, and an insulating material disposed between the first-conductivity-type semiconductor and the second-conductivity-type semiconductor, and that vertically extends with respect to a substrate; a first second-conductivity-type high-concentration semiconductor disposed on the first-conductivity-type semiconductor; a second second-conductivity-type high-concentration semiconductor disposed under the first-conductivity-type semiconductor; a first first-conductivity-type high-concentration semiconductor disposed on the second-conductivity-type semiconductor; a second first-conductivity-type high-concentration semiconductor disposed under the second-conductivity-type semiconductor; a gate insulating material formed around the first pillar; and a gate conductive material formed around the gate insulating material.

摘要翻译： 提供了包括逆变器的高集成度的互补金属氧化物半导体静态随机存取存储器。 逆变器包括：通过集成第一导电型半导体，第二导​​电型半导体和设置在第一导电型半导体与第二导电型半导体之间的绝缘材料形成的第一柱， 并且相对于衬底垂直地延伸; 设置在第一导电型半导体上的第一第二导电型高浓度半导体; 设置在第一导电型半导体下方的第二第二导电型高浓度半导体; 布置在第二导电型半导体上的第一第一导电型高浓度半导体; 设置在第二导电型半导体下方的第二第一导电型高浓度半导体; 围绕所述第一支柱形成的栅极绝缘材料; 以及形成在栅极绝缘材料周围的栅极导电材料。

公开(公告)号：US07940574B2

公开(公告)日：2011-05-10

申请号：US12319782

申请日：2009-01-12

申请人： Fujio Masuoka ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Hiroki Nakamura

IPC分类号： G11C16/04

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  G11C16/10 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/7884 ,  H01L29/7889 ,  H01L29/7926

摘要： It is an object of the present invention to provide a nonvolatile semiconductor memory including memory cells using side walls of island semiconductor layers which avoid lowing of the writing speed and the reading speed. In the nonvolatile semiconductor memory having the nonvolatile semiconductor memory cells each having an island semiconductor layer formed on a semiconductor substrate, the island semiconductor layer having a drain diffusing layer formed on top thereof, a source diffusion layer formed on the lower side thereof, a charge-storage layer formed on a channel area on the side wall interposed between the drain diffusion layer and the source diffusion layer via a gate insulation film, and a control gate formed on the charge-storage layer arranged in matrix, bit lines connected to the drain diffusion layers are arranged in the column direction, control gate lines are arranged in the row direction, and source lines connected to the source diffusion layers are arranged in the column direction, the above-described object is achieved by the nonvolatile semiconductor memory characterized in that common source lines connected to the source lines are formed at every predetermined number of control gate lines, the common source lines are formed of metal, and the common source lines are arranged in the row direction.

摘要翻译： 本发明的目的是提供一种非易失性半导体存储器，其包括使用岛状半导体层的侧壁的存储单元，其避免了写入速度和读取速度的降低。 在具有在半导体基板上形成有岛状半导体层的非易失性半导体存储单元的非易失性半导体存储单元中，形成有在其上侧形成有漏极扩散层的岛状半导体层，形成在其下侧的源极扩散层， 经由栅极绝缘膜插入在漏极扩散层和源极扩散层之间的侧壁上的沟道区上形成的保持层，以及形成在矩阵状的电荷存储层上的控制栅极，连接到漏极的位线 扩散层沿列方向排列，控制栅极线排列成行方向，与源极扩散层连接的源极配线在列方向上，上述目的通过非易失性半导体存储器实现，其特征在于： 连接到源极线的公共源极线以预定数量的控制盖形成 e线，公共源极线由金属形成，并且公共源极线被布置在行方向上。