公开(公告)号：US6023422A

公开(公告)日：2000-02-08

申请号：US163229

申请日：1998-09-29

申请人： Timothy P. Allen ,  James B. Cser

发明人： Timothy P. Allen ,  James B. Cser

IPC分类号： G06N3/063 ,  G11C27/00 ,  G11C16/04

CPC分类号： G11C27/005 ,  G06N3/063 ,  G06N3/0635

摘要： An analog storage array according to the present invention is disposed on a semiconductor substrate. The array is arranged as a plurality of rows and a plurality of columns and includes a plurality of N-channel MOS transistors disposed in the rows and columns in a p-well in the semiconductor substrate. Each of the MOS transistors includes a source, a drain, and a floating gate forming a tunneling junction with a tunneling electrode. An input line is associated with each of the rows in the array. Each input line is connected to the source of each of the N-channel MOS transistors disposed in the row with which the input line is associated. A bias line is associated with each of the rows in the array. Each bias line is capacitively coupled to the floating gate of each of the N-channel MOS transistors disposed in the row with which the bias line is associated. A tunnel line is associated with each of the columns in the array. Each tunnel line connected to the tunneling electrode of each of the N-channel MOS transistors disposed in the column with which the bias line is associated. A current-sum line is associated with each of the columns in the array. Each current-sum line is connected to the drain of each of the N-channel MOS transistors disposed in the column with which the bias line is associated. Circuitry is provided for forward biasing said p-well with respect to the substrate. Circuitry is provided for simultaneously driving a selected one of the bias lines low while driving a selected one of the tunnel lines high, for raising the floating gate voltage of the one of the N-channel MOS transistors common to the selected one of the bias lines and the selected one of the tunnel lines.

摘要翻译： 根据本发明的模拟存储阵列设置在半导体衬底上。 该阵列被布置为多行和多列，并且包括设置在半导体衬底中的p阱中的行和列中的多个N沟道MOS晶体管。 每个MOS晶体管包括源极，漏极和形成与隧穿电极的隧道结的浮置栅极。 输入行与数组中的每一行相关联。 每个输入线连接到与输入线相关联的行中的每个N沟道MOS晶体管的源极。 偏置线与阵列中的每一行相关联。 每个偏置线电容耦合到设置在与偏置线相关联的行中的每个N沟道MOS晶体管的浮置栅极。 隧道线与阵列中的每个列相关联。 每个隧道线连接到设置在与偏置线相关联的列中的每个N沟道MOS晶体管的隧穿电极。 电流和线与阵列中的每个列相关联。 每个电流和线连接到设置在与偏置线相关联的列中的每个N沟道MOS晶体管的漏极。 提供电路用于相对于衬底正向偏置所述p阱。 提供电路，用于同时将所选择的一个偏置线驱动为低电平，同时将所选择的一个隧道线驱动为高电平，以提高所选择的一个偏置线中公共的N沟道MOS晶体管之一的浮置栅极电压 和所选的一条隧道线。

公开(公告)号：US5920310A

公开(公告)日：1999-07-06

申请号：US751182

申请日：1996-11-15

申请人： Federico Faggin ,  Joel A. Seely ,  Timothy P. Allen

发明人： Federico Faggin ,  Joel A. Seely ,  Timothy P. Allen

IPC分类号： G06F1/16 ,  G06F3/033 ,  G08C21/00 ,  G09G5/00

CPC分类号： G06F1/1616 ,  G06F1/169 ,  G06F3/03547 ,  Y10S345/901

摘要： An electronic device is provided making use of a touch pad module to implement user input functions. The electronic device includes a case having a region of thinner cross section than the remaining case side wall for receiving the touch pad module. The case is further provided with a through hole in the area of its thinner cross section for receiving control electronics of the touch pad module enabling the region of thinner cross section to physically support the touch pad module so that the module can be thinner than what is conventionally believed to be necessary to maintain its physical integrity while in use as an input device.

摘要翻译： 提供使用触摸板模块实现用户输入功能的电子设备。 电子设备包括壳体，其具有比用于接收触摸板模块的剩余壳体侧壁更薄的横截面的区域。 该壳体还在其较薄横截面的区域中设有通孔，用于接收触摸板模块的控制电路，使得能够使薄壁截面的区域物理地支撑触摸板模块，使得模块可以比 通常被认为是在使用时作为输入装置保持其物理完整性所必需的。

公开(公告)号：US5541878A

公开(公告)日：1996-07-30

申请号：US267595

申请日：1994-06-27

申请人： John LeMoncheck ,  Timothy P. Allen ,  Gunter Steinbach ,  Carver A. Mead

发明人： John LeMoncheck ,  Timothy P. Allen ,  Gunter Steinbach ,  Carver A. Mead

IPC分类号： G05F1/46 ,  G05F3/24 ,  G11C5/14 ,  G11C11/56 ,  G11C27/00 ,  G11C16/04

CPC分类号： G05F3/247 ,  G05F1/468 ,  G05F3/24 ,  G11C11/56 ,  G11C11/5621 ,  G11C27/005 ,  G11C5/147 ,  G11C16/30 ,  G11C2211/5634 ,  G11C7/16

摘要： A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Circuitry is provided so that all floating gate storage devices can be programmed to their target voltages individually or in parallel. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A transistor structure with a lightly doped drain is provided for control of the tunneling structure. A capacitor is connected to each floating gate node to provide control of the injection structure. A dynamic analog storage element is provided to store the target voltage for the floating gate storage device. A comparator is provided to monitor the floating gate voltage and target voltage and control tunneling and injection. A digital storage device is provided to statically store the output of the comparator. During normal operation of the voltage reference circuit, the voltage comparator is configured as a follower amplifier to buffer the analog voltage output. During normal operation of the bias reference circuit, the current comparator is configured as a current mirror to buffer the analog current output.

摘要翻译： 用于产生用于参考或偏置使用的N个模拟电压信号的电路使用N个模拟浮动栅极存储装置。 提供电路，使得所有浮动栅极存储装置可以单独地或并行地编程到它们的目标电压。 提供电子注入电路用于将电子注入到上面，并且提供隧道结构用于从每个浮动栅极存储装置的浮动栅极去除电子。 提供了具有轻掺杂漏极的晶体管结构，用于控制隧道结构。 电容器连接到每个浮动栅极节点以提供对注入结构的控制。 提供动态模拟存储元件以存储浮动栅极存储装置的目标电压。 提供一个比较器来监控浮动栅极电压和目标电压，并控制隧道和注入。 提供数字存储设备以静态存储比较器的输出。 在电压基准电路正常工作期间，电压比较器被配置为跟随放大器以缓冲模拟电压输出。 在偏置参考电路的正常工作期间，电流比较器被配置为电流镜以缓冲模拟电流输出。

公开(公告)号：US5336936A

公开(公告)日：1994-08-09

申请号：US879964

申请日：1992-05-06

申请人： Timothy P. Allen ,  James B. Cser

发明人： Timothy P. Allen ,  James B. Cser

IPC分类号： G06N3/063 ,  G11C27/00 ,  H03K19/08 ,  H03K19/094

CPC分类号： G11C27/005 ,  G06N3/063 ,  G06N3/0635

摘要： An analog storage array according to the present invention is disposed on a semiconductor substrate. The array is arranged as a plurality of rows and a plurality of columns and includes a plurality of N-channel MOS transistors disposed in the rows and columns in a p-well in the semiconductor substrate. Each of the MOS transistors includes a source, a drain, and a floating gate forming a tunneling junction with a tunneling electrode. An input line is associated with each of the rows in the array. Each input line is connected to the source of each of the N-channel MOS transistors disposed in the row with which the input line is associated. A bias line is associated with each of the rows in the array. Each bias line is capacitively coupled to the floating gate of each of the N-channel MOS transistors disposed in the row with which the bias line is associated. A tunnel line is associated with each of the columns in the array. Each tunnel line connected to the tunneling electrode of each of the N-channel MOS transistors disposed in the column with which the bias line is associated. A current-sum line is associated with each of the columns in the array. Each current-sum line is connected to the drain of each of the N-channel MOS transistors disposed in the column with which the bias line is associated. Circuitry is provided for forward biasing said p-well with respect to the substrate. Circuitry is provided for simultaneously driving a selected one of the bias lines low while driving a selected one of the tunnel lines high, for raising the floating gate voltage of the one of the N-channel MOS transistors common to the selected one of the bias lines and the selected one of the tunnel lines.

摘要翻译： 根据本发明的模拟存储阵列设置在半导体衬底上。 该阵列被布置为多行和多列，并且包括设置在半导体衬底中的p阱中的行和列中的多个N沟道MOS晶体管。 每个MOS晶体管包括源极，漏极和形成与隧穿电极的隧道结的浮置栅极。 输入行与数组中的每一行相关联。 每个输入线连接到与输入线相关联的行中的每个N沟道MOS晶体管的源极。 偏置线与阵列中的每一行相关联。 每个偏置线电容耦合到设置在与偏置线相关联的行中的每个N沟道MOS晶体管的浮置栅极。 隧道线与阵列中的每个列相关联。 每个隧道线连接到设置在与偏置线相关联的列中的每个N沟道MOS晶体管的隧穿电极。 电流和线与阵列中的每个列相关联。 每个电流和线连接到设置在与偏置线相关联的列中的每个N沟道MOS晶体管的漏极。 提供电路用于相对于衬底正向偏置所述p阱。 提供电路，用于同时将所选择的一个偏置线驱动为低电平，同时将所选择的一个隧道线驱动为高电平，以提高所选择的一个偏置线中公共的N沟道MOS晶体管之一的浮置栅极电压 和所选的一条隧道线。

公开(公告)号：US5331215A

公开(公告)日：1994-07-19

申请号：US922535

申请日：1992-07-30

申请人： Timothy P. Allen ,  Janeen D. W. Anderson ,  Carver A. Mead ,  Federico Faggin ,  John C. Platt ,  Michael F. Wall

发明人： Timothy P. Allen ,  Janeen D. W. Anderson ,  Carver A. Mead ,  Federico Faggin ,  John C. Platt ,  Michael F. Wall

IPC分类号： G06N3/063 ,  H01L27/06 ,  H03F1/02 ,  H03F1/30 ,  H03F3/45 ,  H03K19/0948

CPC分类号： H03F1/303 ,  G06N3/063 ,  H01L27/0629 ,  H03F1/0261 ,  H03F3/45479 ,  H03F3/45753 ,  H03F3/45977

摘要： A synaptic array according to the present invention comprises a plurality of electrically-adaptable elements. Electrons may be placed onto and removed from a floating node in each electrically adaptable element associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals generated in response to an adapt signal. The inputs to all synaptic elements in a row are connected to a common row input line. Adapt inputs to all synaptic elements in a column are connected together to a common column adapt line. The current supplied to all amplifiers in a column is commonly provided by a sense line. In order to adapt the synaptic elements in the M row by N column matrix of the present invention, the voltages to which a given column n of the matrix is to be adapted are placed onto the input voltage lines, and the synaptic elements in column n are then simultaneously adapted by assertion of an adapt signal on the adapt line for column n. The vectors of input voltages for adapting successive columns may be placed sequentially onto the row input voltage lines and used to adapt the columns of synaptic elements by assertion of the adapt signals on the appropriate column adapt lines until the entire array is electrically adapted. After each synaptic element has been adapted, the current flowing through it will be maximized when the voltage at the input of the synaptic element equals the voltage to which the synaptic element has been adapted. An electrically adaptable winner-take-all circuit has its inputs connected to the column-sense lines of the array.

摘要翻译： 根据本发明的突触阵列包括多个电适应元件。 可以通过施加产生的第一和第二电控制信号将电子放置在与至少一个MOS绝缘栅场效应晶体管（通常是晶体管的栅极）相关联的每个电适应元件中的浮动节点上并从其移除， 响应于适配信号。 对一行中所有突触元素的输入连接到公共行输入行。 将输入到列中的所有突触元素的调整连接到公共列适应线。 提供给列中所有放大器的电流通常由感测线提供。 为了适应本发明的M行×N列矩阵中的突触元素，要将矩阵的给定列n适应的电压放置在输入电压线上，并且列n中的突触元素 然后通过在第n列的适应线上断言适配信号同时进行调整。 用于适配连续列的输入电压的矢量可以顺序地放置在行输入电压线上，并且用于通过在适当的列适配线上断言适配信号来适应突触元件的列，直到整个阵列电气适配。 在每个突触元件已经适应之后，当突触元件的输入端的电压等于突触元件适应的电压时，流过它的电流将被最大化。 电气适应性的胜者总线电路的输入连接到阵列的列感测线。

公开(公告)号：US5270963A

公开(公告)日：1993-12-14

申请号：US549423

申请日：1990-07-06

申请人： Timothy P. Allen ,  Michael F. Wall ,  Federico Faggin

发明人： Timothy P. Allen ,  Michael F. Wall ,  Federico Faggin

IPC分类号： G06N3/063 ,  G06T5/20 ,  G06G7/16

CPC分类号： G06K9/605 ,  G06K9/00986 ,  G06K9/56 ,  G06N3/0635 ,  G06T5/20

摘要： The present invention is a method and apparatus for performing neighborhood processing operations on an n dimensional processing plane. In a simple, two dimensional, example, an M by N processing plane is successively scanned by rows. The output information from each row is presented on column lines. The analog data resulting from a fixed number of successive scans are temporarily held in a multi-stage analog buffer. A computing array is configured to perform the neighborhood operations or other limited co-operand operations on the shifted data. The computing array examines information from a slice made up of selected numbers of successive rows of the entire array, performs the operations on that portion, and provides a series of output signals representative of the result. The analog buffer is pipelined; information from a new row represents only a single row of new data and the contents of the latch stage containing the oldest information is replaced with this new analog data, causing the information from the transducers of the oldest row to be lost. The operation is then performed on the new slice. This sequence is repeated until all representative slices of the total array have had the neighborhood operations performed on them.

摘要翻译： 本发明是一种用于在n维处理平面上执行邻域处理操作的方法和装置。 在简单的二维例子中，逐行扫描M×N处理平面。 来自每一行的输出信息都列在列线上。 由固定数量的连续扫描产生的模拟数据暂时保存在多级模拟缓冲器中。 计算阵列被配置为对移位的数据执行邻域操作或其他有限的协同操作数操作。 计算阵列检查来自由整个阵列的选定数目的连续行组成的切片的信息，对该部分执行操作，并提供表示结果的一系列输出信号。 模拟缓冲器是流水线的; 来自新行的信息仅代表单行新数据，并且包含最旧信息的锁存级的内容被该新的模拟数据替代，导致来自最旧行的换能器的信息丢失。 然后在新切片上执行操作。 重复该顺序，直到总阵列的所有代表性切片都对它们执行邻域操作。

公开(公告)号：US5146106A

公开(公告)日：1992-09-08

申请号：US650959

申请日：1991-02-05

申请人： Janeen D. W. Anderson ,  Carver A. Mead ,  Timothy P. Allen ,  Michael F. Wall

发明人： Janeen D. W. Anderson ,  Carver A. Mead ,  Timothy P. Allen ,  Michael F. Wall

IPC分类号： G06N3/063 ,  H01L27/06 ,  H03F1/02 ,  H03F1/30 ,  H03F3/45

CPC分类号： H01L27/0629 ,  G06N3/063 ,  H03F1/0261 ,  H03F1/303 ,  H03F3/45479 ,  H03F3/45753 ,  H03F3/45977

摘要： An adaptable MOS winner take all circuit includes a plurality of adaptable current mirrors. Each adaptable current mirror includes a floating node onto which and from which electrons may be transported by control signals and electrical semiconductor structures. Electrons may be placed onto and removed from a floating node associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure.

摘要翻译： 可适应的MOS优胜者采取所有电路包括多个适应电流镜。 每个可适应电流镜包括浮动节点，电子可以通过控制信号和电半导体结构传输到该浮动节点上。 通过施加第一和第二电控制信号，电子可以以模拟的方式放置在与至少一个MOS绝缘栅场效应晶体管（通常是晶体管的栅极）相关联的浮动节点上并从其移除。 第一电控信号控制电子从电子注入结构注入到浮动节点上，第二电控信号通过电子去除结构控制从浮动节点去除电子。

公开(公告)号：US5109261A

公开(公告)日：1992-04-28

申请号：US607158

申请日：1990-10-31

申请人： Carver A. Mead ,  Timothy P. Allen

发明人： Carver A. Mead ,  Timothy P. Allen

IPC分类号： G06N3/063 ,  H01L27/06 ,  H03F1/02 ,  H03F1/30 ,  H03F3/45

CPC分类号： H03F1/0261 ,  G06N3/063 ,  H01L27/0629 ,  H03F1/303 ,  H03F3/45479 ,  H03F3/45753 ,  H03F3/45977

摘要： An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An ultraviolet window above the second capacitor allows the floating node to be charged, by the application of ultraviolet light, to a voltage which effectively cancels the input offset voltage. The ultraviolet window and capacitor electrodes are arranged such that the ultraviolet light may strike only the desired areas of the structure.

摘要翻译： 具有随机输入偏移电压的集成电路放大器是可适应的，使得可以抵消输入偏移电压。 反相输入节点是浮动输入节点，并通过第一电容器耦合到输入信号源。 第二电容器连接在放大器的输出端和浮动节点之间。 第二电容器上方的紫外线窗口允许通过施加紫外线将浮动节点充电到有效地抵消输入偏移电压的电压。 紫外线窗口和电容器电极被布置成使得紫外光可以仅击打结构的期望区域。

公开(公告)号：US5073759A

公开(公告)日：1991-12-17

申请号：US607141

申请日：1990-10-31

申请人： Carver A. Mead ,  Timothy P. Allen

发明人： Carver A. Mead ,  Timothy P. Allen

IPC分类号： G06N3/063 ,  H01L27/06 ,  H03F1/02 ,  H03F1/30 ,  H03F3/45

CPC分类号： G06N3/063 ,  H01L27/0629 ,  H03F1/0261 ,  H03F1/303 ,  H03F3/45479 ,  H03F3/45753 ,  H03F3/45977

摘要： An integrated circuit amplifier having a random input offset voltage is adaptable such that then input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An ultraviolet window above the second capacitor allows the floating node to be charged, by the application of ultraviolet light, to a voltage which effectively cancels the input offset voltage. The ultraviolet window and capacitor electrodes are arranged such that the ultraviolet light may strike only the desired areas of the structure.

摘要翻译： 具有随机输入偏移电压的集成电路放大器是适应性的，从而可以抵消输入偏移电压。 反相输入节点是浮动输入节点，并通过第一电容器耦合到输入信号源。 第二电容器连接在放大器的输出端和浮动节点之间。 第二电容器上方的紫外线窗口允许通过施加紫外线将浮动节点充电到有效地抵消输入偏移电压的电压。 紫外线窗口和电容器电极被布置成使得紫外光可以仅击打结构的期望区域。

公开(公告)号：US5059920A

公开(公告)日：1991-10-22

申请号：US525764

申请日：1990-05-18

申请人： Janeen D. W. Anderson ,  Carver A. Mead ,  Timothy P. Allen ,  Michael F. Wall

发明人： Janeen D. W. Anderson ,  Carver A. Mead ,  Timothy P. Allen ,  Michael F. Wall

IPC分类号： G06N3/063 ,  H01L27/06 ,  H03F1/02 ,  H03F1/30 ,  H03F3/45

CPC分类号： H03F1/0261 ,  G06N3/063 ,  H01L27/0629 ,  H03F1/303 ,  H03F3/45479 ,  H03F3/45753 ,  H03F3/45977

摘要： Electrons may be placed onto and removed from a floating node associated with at least one MOS transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure.An analog MOS integrated circuit comprises an amplifier circuit having a gain much larger than 1. The inverting input into one stage of this amplifier circuit is a floating node forming the gate of at least one MOS transistor. A first capacitor couples an input of the circuit to this floating node. Electrical semiconductor structures are provided for both linearly adding and removing charge from the floating gate, thus allowing the offset voltage of the amplifier to be adapted.An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An electrical learning means allows the floating node to be charged or discharged to a voltage which effectively cancels the input offset voltage.

摘要翻译： 通过施加第一和第二电气控制信号，电子可以以模拟方式放置在与至少一个MOS晶体管（通常是晶体管的栅极）相关联的浮动节点上并从其移除。 第一电控信号控制电子从电子注入结构注入到浮动节点上，第二电控信号通过电子去除结构控制从浮动节点去除电子。 模拟MOS集成电路包括具有大于1的增益的放大器电路。该放大器电路的一级的反相输入是形成至少一个MOS晶体管的栅极的浮动节点。 第一个电容将电路的输入耦合到该浮动节点。 提供电气半导体结构用于从浮动栅极线性地添加和去除电荷，从而允许放大器的偏移电压被适配。 具有随机输入偏移电压的集成电路放大器是可适应的，使得可以抵消输入偏移电压。 反相输入节点是浮动输入节点，并通过第一电容器耦合到输入信号源。 第二电容器连接在放大器的输出端和浮动节点之间。 电学习装置允许浮动节点被充电或放电到有效地抵消输入偏移电压的电压。