公开(公告)号：US20110119368A1

公开(公告)日：2011-05-19

申请号：US13054181

申请日：2008-12-18

申请人： Jun Song ,  Mo Sun

发明人： Jun Song ,  Mo Sun

IPC分类号： G06F15/173

CPC分类号： H04L12/2834 ,  H04L41/5003 ,  H04L47/10

摘要： An apparatus for implementing policy control for home gateway comprises a Co-located Policy Decision Function Entity (PD-FE) for receiving the QoS policy issued by the PD-FE at network side and sending the QoS policy to the home gateway or issuing the QoS policy configured thereon to the home gateway. A method for implementing the policy control for home gateway, the method comprises: the Co-located PD-FE receiving the QoS policy issued by the PD-FE at network side or being configured with the QoS policy; and the Co-located PD-FE issuing the QoS policy to home gateways. With the present invention, the Resource and Admission Control Function (RACF) avoids controlling the home gateway directly or sending the policy to the home gateways in the case that there are a lot of home gateways and all the home gateways are scattered at the edge of the network.

摘要翻译： 用于实现家庭网关策略控制的装置包括一个共同定位的策略决策功能实体（PD-FE），用于接收由网络侧的PD-FE发出的QoS策略，并将QoS策略发送到家庭网关或发出QoS 策略配置在家庭网关上。 一种实现家庭网关策略控制的方法，该方法包括：同时配置PD-FE接收由网络侧PD-FE发布的QoS策略，或配置QoS策略; 以及向家庭网关发布QoS策略的共同配置的PD-FE。 在本发明中，资源和接纳控制功能（RACF）避免了直接控制家庭网关或者在家庭网关很多的情况下向家庭网关发送策略，并且所有家庭网关都在 网络。

公开(公告)号：US20100333171A1

公开(公告)日：2010-12-30

申请号：US12865130

申请日：2008-05-21

申请人： Jianjie You ,  Jun Song ,  Mo Sun

发明人： Jianjie You ,  Jun Song ,  Mo Sun

IPC分类号： G06F21/00 ,  G06F15/173

CPC分类号： H04L12/66 ,  H04L12/6418 ,  H04L47/70 ,  H04L47/781 ,  H04L47/805 ,  H04L63/102 ,  H04L65/1069 ,  H04M15/66 ,  H04W48/02

摘要： The present invention discloses a method for selecting policy decision functional entity in the Resource and Admission Control System. The method includes that: for resource and admission control in the PULL mode, after the Transport Resource Control Function Entity (TRC-FE) receives a resource request message from the Customer Premises Equipment (CPE) or after the Policy Enforcement Function Entity (PE-FE) receives a transport layer signaling sent by CPE, if the TRC-FE or PE-FE is interacting with more than one Policy Decision Functional Entities (PD-FEs), the TRC-FE or the PE-FE may select a PD-FE according to the stored identification information of PD-FE or statically configured PD-FE, and send a resource decision request message to the selected PD-FE. With the application of the present invention, in resource and admission control in the PULL mode, after receiving the resource request initiated by CPE through the transport layer signaling message, the TRC-FE or PE-FE may select the exact PD-FE to implement the resource reservation process, thereby resolving the problem in prior art that during the resource and admission control process the TRC-FE or PE-FE can not select the exact PD-FE to send resource decision requests.

摘要翻译： 本发明公开了一种在资源和准入控制系统中选择策略决策功能实体的方法。 该方法包括：在传输资源控制功能实体（TRC-FE）接收来自客户驻地设备（CPE）的资源请求消息之后，或在策略执行功能实体（PE- FE）接收CPE发送的传输层信令，如果TRC-FE或PE-FE与多个策略决策功能实体（PD-FE）进行交互，则TRC-FE或PE-FE可以选择PD- FE根据存储的PD-FE的标识信息或静态配置的PD-FE，并向所选择的PD-FE发送资源决策请求消息。 随着本发明的应用，在PULL模式的资源和准入控制中，TRC-FE或PE-FE在接收到CPE通过传输层信令消息发起的资源请求后，可以选择准确的PD-FE来实现 资源预留处理，从而解决现有技术中的问题，在资源和准入控制处理期间，TRC-FE或PE-FE不能选择确切的PD-FE来发送资源决策请求。

公开(公告)号：US20050272174A1

公开(公告)日：2005-12-08

申请号：US10862049

申请日：2004-06-04

申请人： Franklin Duan ,  Maureen Ardans ,  Jun Song

发明人： Franklin Duan ,  Maureen Ardans ,  Jun Song

IPC分类号： G01R31/02 ,  G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H01L23/544

CPC分类号： H01L22/34 ,  G01R31/2884

摘要： The present invention is test structures in unused areas of semiconductor integrated circuits and methods for designing the same. In an exemplary aspect of the present invention, a method for placing test structures in a semiconductor integrated circuit includes: (a) detecting a dummy area in a semiconductor integrated circuit, the semiconductor integrated circuit including probe pads on a top metal layer; (b) filling the dummy area with active test cells, the active test cells being connected to one another; and (c) connecting each of the active test cells to the probe pads with a metal line.

摘要翻译： 本发明是半导体集成电路的未使用区域的测试结构及其设计方法。 在本发明的一个示例性方面，一种用于将测试结构放置在半导体集成电路中的方法包括：（a）检测半导体集成电路中的虚拟区域，所述半导体集成电路包括顶部金属层上的探针焊盘; （b）用活性测试单元填充虚拟区域，活性测试单元彼此连接; 和（c）用金属线将每个活性测试单元与探针垫连接。

公开(公告)号：US06555878B2

公开(公告)日：2003-04-29

申请号：US10233764

申请日：2002-09-03

申请人： Jun Song ,  Guang ping Hua ,  Keng-Foo Lo

发明人： Jun Song ,  Guang ping Hua ,  Keng-Foo Lo

IPC分类号： H01L2362

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： Described is a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+/n+ diffusion (anode). A latchup immune circuit is achieved by creating a U-shaped gate structure which is lined with a thick gate oxide—similar to a field oxide—under the poly gate.

摘要翻译： 描述了具有用于IC器件中的ESD保护电路的U形门（UMOS）的MOS栅极控制SCR（UGSCR）结构，其与浅沟槽隔离（STI）和自对准硅化物（自对准硅）制造技术相兼容 。 UMOS门位于p基板中，并且被两侧的n阱包围。 邻近UMOS门的一侧，形成跨越第一n阱的第一n +扩散。 n +扩散以及旁边扩散的p +拾取器形成SCR（晶闸管）的阴极。 在UMOS门的另一侧附近，在第二n阱中形成第二n +和p +扩散。 第二个n +和p +扩散与UMOS门一起形成SCR的阳极和要保护的电路的输入端。 SCR由第一n +扩散/ n阱（阴极），p衬底，第二n阱和第二p + / n +扩散（阳极）形成。 闭锁免疫电路通过在聚栅下形成一个衬有厚栅极氧化物（类似于场氧化物）的U形门结构来实现。

公开(公告)号：US06492242B1

公开(公告)日：2002-12-10

申请号：US09609447

申请日：2000-07-03

申请人： Alex See ,  Cher Liang Randall Cha ,  Shyuz Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

发明人： Alex See ,  Cher Liang Randall Cha ,  Shyuz Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L21/31683

摘要： A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.

摘要翻译： 在高于周围结构所经历的温度的温度下进行的金属氧化物 - 金属电容器结构的高介电常数（高K）层，其特征在于底层金属层的局部氧化， 已经开发 该方法的第一次迭代的特征在于在氧化环境中使用对底层金属层的局部区域进行的激光烧蚀程序。 激光烧蚀过程仅在激光点产生所需的高温，允许在该温度下产生高K层，而不直接暴露于激光烧蚀过程的半导体衬底上的周围结构保持在较低温度 。 第二次迭代的特征在于在氧化环境中进行的底层金属层的特定区域到UV或I线曝光程序，暴露于UV或I线程序的下面的金属层的区域， 通过覆盖光刻板中的透明区域。 该过程还导致在下面的金属层的顶部上形成高K层。

公开(公告)号：US06458632B1

公开(公告)日：2002-10-01

申请号：US09814478

申请日：2001-03-14

申请人： Jun Song ,  Guang Ping Hua ,  Keng-Foo Lo

发明人： Jun Song ,  Guang Ping Hua ,  Keng-Foo Lo

IPC分类号： H01L21332

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： Described is a method of creating a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+/n+ diffusion (anode). A latchup immune circuit is achieved by creating a U-shaped gate structure which is lined with a thick gate oxide—similar to a field oxide—under the poly gate.

摘要翻译： 描述了一种用于在IC器件中的用于ESD保护电路的U形栅极（UMOS）的MOS栅极控制SCR（UGSCR）结构的方法，其与浅沟槽隔离（STI）和自对准硅化物（STI）兼容 自杀）制造技术。 UMOS门位于p基板中，并且被两侧的n阱包围。 邻近UMOS门的一侧，形成跨越第一n阱的第一n +扩散。 n +扩散以及旁边扩散的p +拾取器形成SCR（晶闸管）的阴极。 在UMOS门的另一侧附近，在第二n阱中形成第二n +和p +扩散。 第二个n +和p +扩散与UMOS门一起形成SCR的阳极和要保护的电路的输入端。 SCR由第一n +扩散/ n阱（阴极），p衬底，第二n阱和第二p + / n +扩散（阳极）形成。 闭锁免疫电路通过在聚栅下形成一个衬有厚栅极氧化物（类似于场氧化物）的U形门结构来实现。

公开(公告)号：US06275089B1

公开(公告)日：2001-08-14

申请号：US09482048

申请日：2000-01-13

申请人： Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Lap Chan

发明人： Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Lap Chan

IPC分类号： H03K508

CPC分类号： H01L27/0251

摘要： A transient protection circuit is described which provides electrostatic discharge (ESD) protection for an internal circuit of an IC. The transient protection circuit comprises two Zener diodes connected in series between the input pad and the internal circuit of the IC. A sufficiently large ESD pulse will drive one the two Zener diodes into breakdown mode, thereby reducing the magnitude of the ESD pulse to the remainder of the circuit. Resistive means are paralleled with the Zener diodes to provide a signal path at non-ESD voltages. To help shunt the ESD current away from the internal circuit, PMOS and NMOS transistors are connected in parallel between the positive and the negative voltage supply and their junction is connected to the internal circuit. Negative ESD pulses cause the PMOS transistors to turn on, dumping the ESD energy into the positive voltage supply, while positive ESD pulses cause the NMOS transistors to turn on, dumping the ESD energy into the negative voltage supply. Voltage changes, caused by currents flowing through the resistive means, trigger parasitic SCRs into conduction to provide the bulk of the ESD protection.

摘要翻译： 描述了为IC的内部电路提供静电放电（ESD）保护的瞬态保护电路。 瞬态保护电路包括串联连接在输入焊盘和IC内部电路之间的两个齐纳二极管。 足够大的ESD脉冲将驱动两个齐纳二极管中的一个进入击穿模式，从而将ESD脉冲的幅度减小到电路的其余部分。 电阻性装置与齐纳二极管并联，以在非ESD电压下提供信号路径。 为了有助于将ESD电流从内部电路分流，PMOS和NMOS晶体管并联连接在正电压和负电源之间，它们的结连接到内部电路。 负ESD脉冲导致PMOS晶体管导通，将ESD能量转储到正电压源中，而正的ESD脉冲使NMOS晶体管导通，将ESD能量转储到负电源。 由电流流过电阻的电流引起的电压变化会将寄生的SCR触发导通，以提供大量的ESD保护。

公开(公告)号：US06258677B1

公开(公告)日：2001-07-10

申请号：US09409875

申请日：1999-10-01

申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

IPC分类号： H01L21336

CPC分类号： H01L29/0847 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/76283 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66651

摘要： A method of fabricating a transistor, comprising the following steps. A silicon semiconductor structure having spaced, raised, wedge-shaped dielectric isolation regions defining an active region there between is provided. Epitaxial silicon is grown over the active area to form an SEG region. A dummy gate is formed over the SEG region. Raised epitaxial silicon layers are grown over the SEG region adjacent the dummy gate. The dummy gate is removed, exposing the interior side walls of the raised epitaxial silicon layers. Sidewall spacers are formed on the exposed sidewalls of the raised epitaxial silicon layers. A gate oxide layer is grown over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. A layer of polysilicon is deposited over the structure and is planarized to form a gate conductor over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. The sidewall spacers are removed. No HDP process trench fill is required to form the STIs and no CMP process is required to planarized the STIs.

摘要翻译： 一种制造晶体管的方法，包括以下步骤。 提供了具有限定其间的有源区域的具有间隔开的凸起的楔形介电隔离区域的硅半导体结构。 在活性区域上生长外延硅以形成SEG区域。 在SEG区域上形成一个虚拟门。 凸起的外延硅层生长在与虚拟栅极相邻的SEG区域上。 去除虚拟栅极，暴露凸起的外延硅层的内侧壁。 在凸起的外延硅层的暴露的侧壁上形成侧壁间隔物。 栅极氧化物层生长在SEG区域上并且在凸起的外延硅层的侧壁间隔物之间​​。 在该结构上沉积一层多晶硅，并将其平坦化，以在SEG区域和凸出的外延硅层的侧壁间隔物之间​​形成栅极导体。 去除侧壁间隔物。 不需要HDP工艺沟槽填充来形成STI，并且不需要CMP工艺来平坦化STI。

公开(公告)号：US6045844A

公开(公告)日：2000-04-04

申请号：US140374

申请日：1998-08-26

申请人： Jun Song ,  Randolph M. Beaudry ,  LiHua Fan ,  Weimin Deng ,  Rujida Leepipattanawit

发明人： Jun Song ,  Randolph M. Beaudry ,  LiHua Fan ,  Weimin Deng ,  Rujida Leepipattanawit

IPC分类号： A23B7/144 ,  A23B7/152 ,  A23B55/00 ,  A23L3/3409

CPC分类号： A23B7/144 ,  A23B7/152

摘要： A method for increasing aroma and reducing fungal growth in vegetables and fruits is described. The method uses hexanal in a controlled atmosphere to treat the harvested fruit. The method has been found to be particularly effective for Penicillium sp. and Botrytis sp.

摘要翻译： 描述了一种增加香气和减少蔬菜和水果中的真菌生长的方法。 该方法在可控气氛中使用己醛来处理收获的水果。 已经发现该方法对青霉菌特别有效。 和葡萄孢属（Botrytis sp。）

公开(公告)号：US08381261B2

公开(公告)日：2013-02-19

申请号：US12865130

申请日：2008-05-21

申请人： Jianjie You ,  Jun Song ,  Mo Sun

发明人： Jianjie You ,  Jun Song ,  Mo Sun

IPC分类号： G06F21/00

CPC分类号： H04L12/66 ,  H04L12/6418 ,  H04L47/70 ,  H04L47/781 ,  H04L47/805 ,  H04L63/102 ,  H04L65/1069 ,  H04M15/66 ,  H04W48/02

摘要： The present invention discloses a method for selecting policy decision functional entity in the Resource and Admission Control System. The method includes that: for resource and admission control in the PULL mode, after the Transport Resource Control Function Entity (TRC-FE) receives a resource request message from the Customer Premises Equipment (CPE) or after the Policy Enforcement Function Entity (PE-FE) receives a transport layer signaling sent by CPE, if the TRC-FE or PE-FE is interacting with more than one Policy Decision Functional Entities (PD-FEs), the TRC-FE or the PE-FE may select a PD-FE according to the stored identification information of PD-FE or statically configured PD-FE, and send a resource decision request message to the selected PD-FE. With the application of the present invention, in resource and admission control in the PULL mode, after receiving the resource request initiated by CPE through the transport layer signaling message, the TRC-FE or PE-FE may select the exact PD-FE to implement the resource reservation process, thereby resolving the problem in prior art that during the resource and admission control process the TRC-FE or PE-FE can not select the exact PD-FE to send resource decision requests.

摘要翻译： 本发明公开了一种在资源和准入控制系统中选择策略决策功能实体的方法。 该方法包括：在传输资源控制功能实体（TRC-FE）接收到来自客户驻地设备（CPE）的资源请求消息或策略执行功能实体（PE- FE）接收CPE发送的传输层信令，如果TRC-FE或PE-FE与多个策略决策功能实体（PD-FE）进行交互，则TRC-FE或PE-FE可以选择PD- FE根据存储的PD-FE的标识信息或静态配置的PD-FE，并向所选择的PD-FE发送资源决策请求消息。 随着本发明的应用，在PULL模式的资源和准入控制中，TRC-FE或PE-FE在接收到CPE通过传输层信令消息发起的资源请求后，可以选择准确的PD-FE来实现 资源预留处理，从而解决现有技术中的问题，在资源和准入控制处理期间，TRC-FE或PE-FE不能选择确切的PD-FE来发送资源决策请求。