公开(公告)号：US06784548B2

公开(公告)日：2004-08-31

申请号：US10309272

申请日：2002-12-04

申请人： Hiroyuki Kouno ,  Toshio Kumamoto ,  Takahiro Miki ,  Hisayasu Satoh

发明人： Hiroyuki Kouno ,  Toshio Kumamoto ,  Takahiro Miki ,  Hisayasu Satoh

IPC分类号： H01L2348

CPC分类号： H01L27/08 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76838 ,  H01L21/823437 ,  H01L23/5227 ,  H01L23/528 ,  H01L29/42372 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A gate electrode has a relatively long gate length of e.g., about 10 &mgr;m. In a region immediately above the gate electrode which is sandwiched between first-layer metals provided is a metal dummy pattern having a width in the first direction and extending in the second direction perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern in the second direction is equal to a geometric center of the gate electrode in the second direction. This maintains the symmetry in shape of the metal dummy pattern as viewed from the gate electrode. Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.

摘要翻译： 栅电极具有例如约10μm的较长栅极长度。 在夹在所提供的第一层金属之间的栅电极正上方的区域是具有第一方向的宽度并且沿与栅极长度方向（电流方向）垂直的第二方向延伸的金属虚设图案。 此外，第二方向上的金属虚设图案的几何中心等于栅电极在第二方向上的几何中心。 这保持了从栅电极观察时的金属虚设图形的对称性。 这种结构可以使多种元素的特性劣化，同时保持金属CMP的基本效果。

公开(公告)号：US06573588B1

公开(公告)日：2003-06-03

申请号：US10278943

申请日：2002-10-24

申请人： Toshio Kumamoto ,  Takashi Okuda ,  Yasuo Morimoto

发明人： Toshio Kumamoto ,  Takashi Okuda ,  Yasuo Morimoto

IPC分类号： H01L2900

CPC分类号： H01L29/92 ,  H01L29/94

摘要： A P well region formed on a buried N well region and a n+ active region that are connected each other through a lead wire, serve as one terminal T1, and a gate electrode and a buried N well region that are connected each other through a leading N well region and a lead wire, serve as the other terminal T2. Thereby, the voltage dependence of capacitance C1 formed between the gate electrode and the n+ active region is canceled out with the voltage dependence of capacitance C2 formed between the P well region and the buried N well region.

摘要翻译： AP阱区域形成在通过引线彼此连接的掩埋N阱区域和n +有源区域上，用作一个端子T1，以及通过前导N相互连接的栅电极和掩埋N阱区域 井区和导线，作为另一个终端T2。 由此，在P阱区域和掩埋N阱区域之间形成的电容C2的电压依赖性抵消在栅电极和n +有源区域之间形成的电容C1的电压依赖性。

公开(公告)号：US5936434A

公开(公告)日：1999-08-10

申请号：US912813

申请日：1997-08-19

申请人： Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki ,  Takashi Okuda

发明人： Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki ,  Takashi Okuda

IPC分类号： H03M1/34 ,  H03F3/45 ,  H03K5/08 ,  H03K5/24 ,  H03K5/153

CPC分类号： H03K5/249 ,  H03K5/2481

摘要： An object is to obtain a voltage comparator capable of high-accuracy voltage comparison. An input voltage (VIN) and a reference voltage (VREF) are connected to one electrode of a capacitor (C1) through switches (S1) and (S2), respectively. The other electrode of the capacitor (C1) is connected to the input portion of an inverter (INV1). The output portion of the inverter (INV1) is connected to the input portion of an inverter (INV3) and is also fed back to the input through a switch (S3). An inverter (INV11) is further connected in parallel with the inverter (INV1), wherein the input/output characteristics of the inverters (INV1, INV3 and INV11) are set equal.

摘要翻译： 目的是获得能够进行高精度电压比较的电压比较器。 分别通过开关（S1）和（S2）将输入电压（VIN）和参考电压（VREF）连接到电容器（C1）的一个电极。 电容器（C1）的另一个电极连接到逆变器（INV1）的输入部分。 逆变器（INV1）的输出部分连接到逆变器（INV3）的输入部分，并通过开关（S3）反馈到输入端。 反相器（INV11）进一步与反相器（INV1）并联连接，其中反相器（INV1，INV3和INV11）的输入/输出特性被设定为相等。

公开(公告)号：US5554989A

公开(公告)日：1996-09-10

申请号：US241422

申请日：1994-05-11

申请人： Toshio Kumamoto ,  Takahiro Miki

发明人： Toshio Kumamoto ,  Takahiro Miki

IPC分类号： H03M1/36 ,  H03M1/06

CPC分类号： H03M1/0682 ,  H03M1/368

摘要： Voltage comparators C.sub.1 -C.sub.N for comparing a first differential reference voltage obtained by dividing a first reference voltage V.sub.RT and a second reference voltage V.sub.RB by ladder resistors r.sub.1 -r.sub.N+1 and a second differential reference input voltage formed by a third voltage V.sub.i and a fourth voltage V.sub.i are arranged in first to N/2 and (N/2+1)-th to N-th voltage comparator rows in a folded manner and wiring area can be reduced as a result.

摘要翻译： 电压比较器C1-CN，用于比较通过用梯形电阻器r1-rN + 1划分第一参考电压VRT和第二参考电压VRB获得的第一差分参考电压和由第三电压Vi和第四电压形成的第二差分参考输入电压 电压+ E，ovs Vi + EE以折叠方式排列在第一至N / 2和（N / 2 + 1）至第N电压比较器行中，结果可以减少配线区域。

公开(公告)号：US5396131A

公开(公告)日：1995-03-07

申请号：US988599

申请日：1992-12-10

申请人： Takahiro Miki ,  Toshio Kumamoto

发明人： Takahiro Miki ,  Toshio Kumamoto

IPC分类号： H03F3/45 ,  H03K3/2885 ,  H03K5/08 ,  H03K5/24 ,  H03M1/14 ,  H03M1/34 ,  H03M1/36

CPC分类号： H03K3/2885 ,  H03K5/2418 ,  H03K5/2427 ,  H03M1/362

摘要： Disclosed is a high-speed A/D converter (15) including an improved differential amplifier circuit. Each comparator (61) provided in the A/D converter directly receives a complementary or differential analog input voltage to be converted. A differential amplifier circuit provided in each comparator compares an applied analog input voltage difference and an applied reference voltage difference. A binary signal indicative of a comparison result is applied to an encoder (4) through a binarization circuit. An analog input voltage which is not to be converted is directly applied to the comparator, that is, to the differential amplifier circuit through none of resistor elements and components, whereby conversion time delay is prevented.

摘要翻译： 公开了一种包括改进的差分放大器电路的高速A / D转换器（15）。 设置在A / D转换器中的每个比较器（61）直接接收待转换的互补或差分模拟输入电压。 在每个比较器中提供的差分放大器电路比较所施加的模拟输入电压差和施加的参考电压差。 指示比较结果的二进制信号通过二值化电路施加到编码器（4）。 将不转换的模拟输入电压直接施加到比较器，即不通过电阻元件和元件对差分放大器电路施加，从而防止转换时间延迟。

公开(公告)号：US5099146A

公开(公告)日：1992-03-24

申请号：US539828

申请日：1990-06-18

申请人： Takahiro Miki ,  Shiro Hosotani ,  Toshio Kumamoto

发明人： Takahiro Miki ,  Shiro Hosotani ,  Toshio Kumamoto

IPC分类号： H01L29/78 ,  H03K3/22 ,  H03K5/08 ,  H03K17/30 ,  H03K17/687 ,  H03M1/36

CPC分类号： H03K5/086 ,  H01L2924/0002

摘要： In a controlled threshold type electric device having first and second transistors and a differential amplifier which receives a reference input voltage, a voltage corresponding to the threshold voltage of the first transistor itself is applied to the differential amplifier as a feedback input voltage. The differential amplifier compares the received feed back input voltage with the reference input voltage and applies a control voltage to the backgate of the first transistor so that the threshold value of the first transistor converges to a desired value. This control voltage is also applied to the backgate of the second transistor so that the threshold voltage of the second transistor also converges to a desired value. Since the voltage corresponding to the threshold value of the first transistor is applied to the differential amplifier, an accurate feed back control is made. Further, since the differential amplifier can be manufactured through the MOS standard process, the manufacturing cost can be reduced.

摘要翻译： 在具有第一和第二晶体管的受控阈值型电器件和接收参考输入电压的差分放大器中，将与第一晶体管本身的阈值电压相对应的电压作为反馈输入电压施加到差分放大器。 差分放大器将接收的反馈输入电压与参考输入电压进行比较，并将控制电压施加到第一晶体管的背栅极，使得第一晶体管的阈值收敛到期望值。 该控制电压也被施加到第二晶体管的背栅，使得第二晶体管的阈值电压也收敛到期望值。 由于将对应于第一晶体管的阈值的电压施加到差分放大器，因此进行精确的反馈控制。 此外，由于可以通过MOS标准工艺制造差分放大器，所以可以降低制造成本。

公开(公告)号：US08330199B2

公开(公告)日：2012-12-11

申请号：US12570650

申请日：2009-09-30

申请人： Masaomi Kamakura ,  Toshio Kumamoto ,  Takashi Okuda

发明人： Masaomi Kamakura ,  Toshio Kumamoto ,  Takashi Okuda

IPC分类号： H03F3/45 ,  H03F3/04 ,  H01C1/012

CPC分类号： H03F3/45475 ,  H01L27/0802 ,  H01L28/20 ,  H03F2203/45528 ,  H03F2203/45594 ,  H03F2203/45602

摘要： To eliminate the substrate voltage dependences of the respective resistance values of resistor elements, in the resistor elements coupled in series to each other over respective substrate regions, the ends of the resistor elements are coupled to the corresponding substrate regions by respective bias wires such that respective average potentials between the substrate regions of the resistor elements and the corresponding resistor elements have opposite polarities, and equal magnitudes.

摘要翻译： 为了消除电阻元件的相应电阻值的衬底电压依赖性，在电阻元件中在各个衬底区域上彼此串联耦合的电阻器元件中，电阻器元件的端部通过相应的偏置线耦合到相应的衬底区域， 电阻元件的基板区域和对应的电阻元件之间的平均电位具有相反的极性和相等的幅度。

公开(公告)号：US07847714B2

公开(公告)日：2010-12-07

申请号：US12411142

申请日：2009-03-25

申请人： Toshio Kumamoto ,  Takashi Okuda ,  Tatsuo Sengoku ,  Akira Kitaguchi

发明人： Toshio Kumamoto ,  Takashi Okuda ,  Tatsuo Sengoku ,  Akira Kitaguchi

IPC分类号： H03M1/20

CPC分类号： H03M3/328 ,  H03M3/33 ,  H03M3/43 ,  H03M3/452

摘要： There is provided a technique for reducing the adverse effect of idle tones in the channels in a ΔΣ-type A/D converter including a plurality of channels for converting analog input signals into digital signals. The ΔΣ-type A/D converter includes an L channel for converting a left analog input signal into a digital signal and an R channel for converting a right analog input signal into a digital signal. Each of the L channel and the R channel includes a DC dither circuit for generating a DC addition voltage for shifting the frequency of an idle tone. In the L channel and the R channel, DC addition voltages generated by DC dither circuits are different from each other.

摘要翻译： 提供了一种用于减少包括用于将模拟输入信号转换为数字信号的多个通道的＆Dgr＆amp; S型A / D转换器中的通道中的空闲音调的不利影响的技术。 ＆amp; S＆amp; S型A / D转换器包括用于将左模拟输入信号转换为数字信号的L通道和用于将右模拟输入信号转换为数字信号的R通道。 L沟道和R沟道中的每一个包括用于产生用于移动空闲频率的频率的DC附加电压的DC抖动电路。 在L沟道和R沟道中，由DC抖动电路产生的直流相加电压彼此不同。

公开(公告)号：US07710304B2

公开(公告)日：2010-05-04

申请号：US12178244

申请日：2008-07-23

申请人： Toshio Kumamoto ,  Takashi Okuda

发明人： Toshio Kumamoto ,  Takashi Okuda

IPC分类号： H03M1/12

CPC分类号： H03M3/376 ,  H03M3/452

摘要： In an A/D converter including a switched capacitor integration circuit, to suppress an effect of a noise generated in the switched capacitor circuit while suppressing increase in a forming area of the circuit. A first-stage integrator of a differential input type A/D converter includes first and second switched capacitor circuits, and includes a noise cancel circuit for generating a noise cancel signal to cancel a kickback noise generated due to switching operation thereof.

摘要翻译： 在包括开关电容器积分电路的A / D转换器中，抑制在开关电容器电路中产生的噪声的影响，同时抑制电路的形成区域的增加。 差分输入型A / D转换器的第一级积分器包括第一和第二开关电容器电路，并且包括用于产生噪声消除信号的噪声消除电路，以消除由于其切换操作而产生的反冲噪声。

公开(公告)号：US07276776B2

公开(公告)日：2007-10-02

申请号：US11013514

申请日：2004-12-17

申请人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

发明人： Takashi Okuda ,  Yasuo Morimoto ,  Yuko Maruyama ,  Toshio Kumamoto

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.

摘要翻译： 半导体器件包括：包括主表面的半导体衬底; 多个第一互连形成在形成在主表面上并沿预定方向延伸的电容形成区域中; 多个第二互连，每个相邻于位于电容形成区域的边缘处的第一互连，沿预定方向延伸并具有固定电位; 以及绝缘层，形成在主表面上，并且填充在每个第一互连之间以及第一互连和第二互连之间相邻。 第一互连和第二互连在平行于主表面的平面中以基本相等的间隔定位，并且被定位成在基本上垂直于预定方向的方向上对准。