公开(公告)号：US06703957B2

公开(公告)日：2004-03-09

申请号：US10143878

申请日：2002-05-14

申请人： Yasuo Morimoto ,  Toshio Kumamoto ,  Takashi Okuda ,  Takahiro Miki

发明人： Yasuo Morimoto ,  Toshio Kumamoto ,  Takashi Okuda ,  Takahiro Miki

IPC分类号： H03M166

CPC分类号： H03M1/0614 ,  H03K5/01 ,  H03K5/133 ,  H03M1/822 ,  H03M3/372 ,  H03M3/506

摘要： When forming PDM pulses by a D/A converter in accordance with digital signals, the D/A converter causes at least one of the rising stage and the falling stage of each of the PDM pulses to change stepwise. In addition, when forming PWM pulses by another D/A converter, the D/A converter causes at least one of the rising stage and the falling stage of each of the PWM pulses to change stepwise.

摘要翻译： 当通过D / A转换器根据数字信号形成PDM脉冲时，D / A转换器使得每个PDM脉冲的上升沿和下降沿中的至少一个逐步改变。 此外，当由另一个D / A转换器形成PWM脉冲时，D / A转换器使每个PWM脉冲的上升沿和下降沿中的至少一个逐步改变。

公开(公告)号：US4900952A

公开(公告)日：1990-02-13

申请号：US303778

申请日：1989-01-27

申请人： Shiro Hosotani ,  Takahiro Miki ,  Toshio Kumamoto

发明人： Shiro Hosotani ,  Takahiro Miki ,  Toshio Kumamoto

IPC分类号： G01R19/165 ,  H03K5/08 ,  H03K5/24

CPC分类号： H03K5/249

摘要： The voltage comparison apparatus of the invention features a timing control of clocks by which individual switches are ON/OFF controlled so that before a preceding amplifier circuit goes into comparison mode from auto zero mode, a successive amplifier circuit may go into auto zero mode from comparison mode, or before the preceding amplifier circuit goes into auto zero mode from comparison mode, the successive amplifier circuit may go into comparison mode from auto zero mode, whereby before the preceding amplifier circuit undergoes transition from the auto zero mode to the comparison mode, the successive amplifier circuit goes into the auto zero mode from the comparison mode, or before the preceding amplifier circuit undergoes transition from the comparison mode to the auto zero mode, the successive amplifier circuit goes into the comparison mode from the auto zero mode, and even when considerable variation occurs in input voltage difference during each clock cycle or clock time lags occurs, stable operation can be assured.

摘要翻译： 本发明的电压比较装置具有对各个开关进行ON / OFF控制的时钟的定时控制，使得在前一放大器电路从自动归零模式进入比较模式之前，连续的放大器电路可以从比较进入自动零模式 模式，或在比较模式之前的前一放大器电路进入自动归零模式之前，连续的放大器电路可以从自动调零模式进入比较模式，由此在之前的放大器电路经历从自动调零模式转换到比较模式之前， 连续放大器电路从比较模式进入自动归零模式，或者在前一放大器电路从比较模式转换到自动归零模式之前，连续放大器电路从自动归零模式进入比较模式，甚至当 在每个时钟周期或时钟时间滞后时，输入电压差异会发生相当大的变化 遏制，稳定运行可以放心。

公开(公告)号：US06522007B2

公开(公告)日：2003-02-18

申请号：US09974856

申请日：2001-10-12

申请人： Hiroyuki Kouno ,  Toshio Kumamoto ,  Takahiro Miki ,  Hisayasu Satoh

发明人： Hiroyuki Kouno ,  Toshio Kumamoto ,  Takahiro Miki ,  Hisayasu Satoh

IPC分类号： H01L2348

CPC分类号： H01L27/08 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76838 ,  H01L21/823437 ,  H01L23/5227 ,  H01L23/528 ,  H01L29/42372 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A gate electrode has a relatively long gate length of e.g., about 10 &mgr;m. In a region immediately above the gate electrode which is sandwiched between first-layer metals provided is a metal dummy pattern having a width in the first direction and extending in the second direction perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern in the second direction is equal to a geometric center of the gate electrode in the second direction. This maintains the symmetry in shape of the metal dummy pattern as viewed from the gate electrode. Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.

摘要翻译： 栅电极具有例如约10μm的较长栅极长度。 在夹在所提供的第一层金属之间的栅电极正上方的区域是具有第一方向的宽度并且沿与栅极长度方向（电流方向）垂直的第二方向延伸的金属虚设图案。 此外，第二方向上的金属虚设图案的几何中心等于栅电极在第二方向上的几何中心。 这保持了从栅电极观察时的金属虚设图形的对称性。 这样的结构可以使多个元件的特性劣化，同时保持金属CMP的基本效果。

公开(公告)号：US5345237A

公开(公告)日：1994-09-06

申请号：US77932

申请日：1993-06-18

申请人： Hiroyuki Kouno ,  Takahiro Miki ,  Toshio Kumamoto

发明人： Hiroyuki Kouno ,  Takahiro Miki ,  Toshio Kumamoto

IPC分类号： H03F3/45 ,  H03M1/14 ,  H03M1/36 ,  H03M1/34

CPC分类号： H03M1/146 ,  H03F3/45071 ,  H03M1/365

摘要： The present invention is directed to improvement of a differential amplifier an its peripheral components employed in an A/D converter to enhance an accuracy of the A/D converter. The differential amplifier has an amplifying element comprised of a pair of differential transistors Q1 and Q2, emitter resistances 2a and 2b, and collector resistances 2c and 2d. The differential amplifier has transistors Q3 and Q4 constituting an emitter follower for applying an output amplified in the differential amplifying element to the outside. The differential amplifier includes transistors Q5 and Q6 having their respective base electrodes connected to input terminals 4a and 4b and serially connected to the transistors Q3 and Q4, and resistances 2e and 2f interposed between emitter electrodes of the transistors Q5 and Q6 so as to relieve any influence of variations in base-emitter voltages of the transistors Q3 and Q4. Effectively an output from the emitter follower can be improved and a gain of the differential amplifier and linearity can be also improved.

摘要翻译： 本发明旨在改进差分放大器及其在A / D转换器中采用的周边部件，以提高A / D转换器的精度。 差分放大器具有由一对差分晶体管Q1和Q2，发射极电阻2a和2b以及集电极电阻2c和2d组成的放大元件。 差分放大器具有构成射极跟随器的晶体管Q3和Q4，用于将在差分放大元件中放大的输出施加到外部。 差分放大器包括具有连接到输入端子4a和4b并且串联连接到晶体管Q3和Q4的各自的基极的晶体管Q5和Q6，以及夹在晶体管Q5和Q6的发射极之间的电阻2e和2f，以便减轻任何 晶体管Q3和Q4的基极 - 发射极电压变化的影响。 有效地提高了射极跟随器的输出，并且还可以提高差分放大器的增益和线性度。

公开(公告)号：US5283581A

公开(公告)日：1994-02-01

申请号：US952413

申请日：1992-09-29

申请人： Takahiro Miki ,  Toshio Kumamoto

发明人： Takahiro Miki ,  Toshio Kumamoto

IPC分类号： H03M1/14 ,  G06G7/14 ,  H03M1/16 ,  H03M1/74

CPC分类号： H03M1/167 ,  G06G7/14 ,  H03M1/747

摘要： An analog voltage subtracting circuit for calculating a difference between an analog input voltage and a voltage drop caused by a load includes an analog voltage generator 7 for generating an analog voltage, a load 3 having one end connected to an output of the analog voltage generator 7 and the other end connected to an output terminal 2, and a D/A converter 6 applying a positive output current Iout for generating a desired voltage drop at said the other end 4 of the load 3 and for applying a complementary output current Iout complementary to the positive output current Iout to said one end of the load 3. By this structure, a constant current of Iout+Iout flows at said one end 4 of the load 3, and therefore linear output can be provided.

摘要翻译： 用于计算模拟输入电压和由负载引起的电压降之间的差的模拟电压减去电路包括用于产生模拟电压的模拟电压发生器7，一端连接到模拟电压发生器7的输出的负载3 并且另一端连接到输出端子2和D / A转换器6，D / A转换器6施加正输出电流Iout，用于在负载3的另一端4处产生期望的电压降，并且用于施加互补的输出电流I ）与负载3的所述一端的正输出电流Iout互补。通过这种结构，Iout + I（OVS）的恒定电流在负载3的所述一端4处流动，因此可以提供线性输出。

公开(公告)号：US06069579A

公开(公告)日：2000-05-30

申请号：US131238

申请日：1998-08-07

申请人： Masao Ito ,  Takeshi Shigenobu ,  Toshio Kumamoto ,  Takahiro Miki ,  Hiroshi Komurasaki

发明人： Masao Ito ,  Takeshi Shigenobu ,  Toshio Kumamoto ,  Takahiro Miki ,  Hiroshi Komurasaki

IPC分类号： H03M1/14 ,  H03M1/20 ,  H03M1/36 ,  H03M1/12

CPC分类号： H03M1/205 ,  H03M1/141

摘要： An A/D converter simplifies its circuit configuration without deteriorating accuracy in A/D conversion. A circuit is formed of a folding and interpolation type. A gain-variable pre-amplifier group 11 amplifies each of reference voltages Vref1 to VrefN and an analog input voltage Vin, to output the result to a folding amplifier group 12, while a gain-variable pre-amplifier group 21 amplifies each of reference voltages Vrr1 to VrrJ and the analog input voltage Vin, to output the result to a comparator group 24. Each of pre-amplifiers constituting the gain-variable pre-amplifier groups 11 and 21 has an amplification factor that varies in upper and lower comparison periods according to a clock control signal .PHI.cnt.

摘要翻译： A / D转换器简化了其电路配置，而不会降低A / D转换的精度。 电路由折叠和内插形式组成。 增益可变前置放大器组11放大每个参考电压Vref1至VrefN和模拟输入电压Vin，以将结果输出到折叠放大器组12，而增益可变的前置放大器组21放大每个参考电压 Vrr1至VrrJ和模拟输入电压Vin，将结果输出到比较器组24.构成增益可变前置放大器组11和21的每个前置放大器具有在上和下比较周期内变化的放大系数， 到时钟控制信号PHI cnt。

公开(公告)号：US5625308A

公开(公告)日：1997-04-29

申请号：US557556

申请日：1995-11-14

申请人： Osamu Matsumoto ,  Takahiro Miki ,  Toshio Kumamoto

发明人： Osamu Matsumoto ,  Takahiro Miki ,  Toshio Kumamoto

IPC分类号： H03M1/34 ,  H03K3/0233 ,  H03K3/356 ,  H03K3/289

CPC分类号： H03K3/35606 ,  H03K3/356034 ,  H03K3/35613

摘要： A high-performance differential latch circuit which includes a differential amplifier circuit comprised of an NMOS transistor (27) serving as a constant current source, PMOS transistors (3, 4) and NMOS transistors (23,24), a latch circuit comprised of NMOS transistors (25, 26), and a switch circuit comprised of NMOS transistors (21,22,28) for alternately operating the differential amplifying function and latch function, the transistor (27) serving as the constant current source having a drain terminal directly connected to the transistors (23,24) and a source terminal directly connected to a ground voltage (2), whereby the differential latch circuit differentially amplifies the signals without the loss of the constant current source function during the differential amplification.

摘要翻译： 一种高性能差分锁存电路，包括由用作恒流源的NMOS晶体管（27），PMOS晶体管（3,4）和NMOS晶体管（23,24）组成的差分放大器电路，由NMOS 晶体管（25,26）以及由NMOS晶体管（21,22,28）组成的用于交替操作差分放大功能和锁存功能的开关电路，用作恒流源的晶体管（27）具有直接连接的漏极端子 到晶体管（23,24）和直接连接到接地电压（2）的源极端子，由此差分锁存电路在差分放大期间不损失恒定电流源功能而差分放大信号。

公开(公告)号：US5539406A

公开(公告)日：1996-07-23

申请号：US264676

申请日：1994-06-23

申请人： Hiroyuki Kouno ,  Toshio Kumamoto ,  Takahiro Miki

发明人： Hiroyuki Kouno ,  Toshio Kumamoto ,  Takahiro Miki

IPC分类号： H03M1/06 ,  H03M1/14 ,  H03M1/36 ,  H03M1/76 ,  H03M1/12

CPC分类号： H03M1/146 ,  H03M1/0682 ,  H03M1/365 ,  H03M1/765

摘要： An upper comparator group compares an analog signal with upper reference potentials applied from upper ladder resistance network. A switch group outputs the predetermined intermediate reference potential of the ladder resistance network to an analog subtracting circuit in response to the upper comparison results. The analog subtracting circuit subtracts the intermediate reference potential from the analog signal for producing an input signal for use in the lower side. A lower ladder resistance network outputs lower reference potentials obtained by dividing by resistors constant static intermediate reference potentials of the ladder resistance network applied from a differential amplifying circuit. A lower comparator group compares the lower reference potentials with the input signal for lower comparison. The upper and the lower comparison results are converted into a digital signal by upper and the lower encoders and the adding/subtracting circuit.

摘要翻译： 上比较器组将模拟信号与上梯形电阻网络施加的较高参考电位进行比较。 开关组响应于较高的比较结果将梯形电阻网络的预定中间参考电位输出到模拟减法电路。 模拟减法电路从用于产生用于下侧的输入信号的模拟信号中减去中间参考电位。 下梯形电阻网络通过将电阻除以由差分放大电路施加的梯形电阻网络的恒定静态中间参考电位而得到的较低参考电位。 较低的比较器组将较低的参考电位与输入信号进行比较，用于较低的比较。 上下比较结果由上下编码器和加减电路转换成数字信号。

公开(公告)号：US5995031A

公开(公告)日：1999-11-30

申请号：US968207

申请日：1997-11-12

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki

IPC分类号： H03M1/10 ,  H03M1/06 ,  H03M1/74 ,  H03M1/66

CPC分类号： H03M1/0663 ,  H03M1/747 ,  H03M3/464 ,  H03M3/502

摘要： A multi-bit D/A converter which improves the linearity of an analog output relative to a digital input is provided. A switch control circuit (1) turns on D some of a plurality of switches (S1 to SM) which are arranged in ascending order starting with a switch determined by a start position determination circuit (3) and turns off the remaining switches, the number of switches turned on being dependent on a digital signal (DIG). The start position determination circuit (3) sequentially changes the switches (S1, S3, S5, . . . ) serving as a selection start position to determine the selection start position for each input of the digital signal (DIG) provided in synchronism with a clock signal (CLK).

摘要翻译： 提供了一种提高模拟输出相对于数字输入的线性度的多位D / A转换器。 开关控制电路（1）接通D开始的开关位置确定电路（3）确定的开关的升序排列的多个开关（S1至SM）中的一些，并且关闭其余的开关 开关依赖于数字信号（DIG）。 开始位置确定电路（3）顺序地改变用作选择开始位置的开关（S1，S3，S5 ...），以确定与设置的与数字信号（DIG）同步的数字信号（DIG）的每个输入的选择开始位置 时钟信号（CLK）。

公开(公告)号：US5629700A

公开(公告)日：1997-05-13

申请号：US552016

申请日：1995-11-02

申请人： Toshio Kumamoto ,  Osamu Matsumoto ,  Takahiro Miki ,  Masao Ito ,  Takashi Okuda

发明人： Toshio Kumamoto ,  Osamu Matsumoto ,  Takahiro Miki ,  Masao Ito ,  Takashi Okuda

IPC分类号： H03M1/14 ,  H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/16 ,  H03M1/44 ,  H03M1/34

CPC分类号： H03M1/002 ,  H03M1/0682 ,  H03M1/069 ,  H03M1/1215 ,  H03M1/167

摘要： An A/D converter block A/D1 converts an analog input signal Vin to a digital signal and outputs its D/A output. First SH/SUBT7, 8 sample the signal Vin and a voltage VRM at the same timing with said A/D conversion and output the results of subtraction of the respective sampling values and the D/A output during holding, respectively. The both results of subtraction are several tens mV and there is no need of taking account of the linearity of a differential amplifier DIFF11. During the sampling, a circuit SHR1 outputs the differential voltages between each reference tap voltage taken out from specific 2 points of the ladder-type resistor in the A/D converter block A/D1 and the voltage VRM while a differential amplifier DIFF12 applies the reference voltages to the next A/D converter block A/D2. Such operations are performed in each stage. Thus, it becomes possible to make any S/H circuit and amplifier of excellent linearity in the first stage unnecessary to reduce the electric power consumption.

摘要翻译： A / D转换器模块A / D1将模拟输入信号Vin转换为数字信号并输出​​其D / A输出。 第一SH / SUBT7,8以与所述A / D转换相同的定时采样信号Vin和电压VRM，并分别输出相应采样值和保持期间的D / A输出的结果。 减法的结果都是几十mV，不需要考虑差分放大器DIFF11的线性度。 在采样期间，电路SHR1输出从A / D转换器模块A / D1中的梯形电阻器的特定2点取出的每个参考分接电压与电压VRM之间的差分电压，而差分放大器DIFF12施加参考 电压到下一个A / D转换器模块A / D2。 这样的操作在每个阶段进行。 因此，可以使得在第一级中具有优异线性度的任何S / H电路和放大器不必减少电力消耗。