公开(公告)号：US5950937A

公开(公告)日：1999-09-14

申请号：US197535

申请日：1998-11-23

申请人： Akihito Iwai ,  Hiroshi Wada ,  Katsumi Matsumoto ,  Sosuke Naito ,  Yoshihiko Imai ,  Hideki Nakamura ,  Hiroaki Tanaka

发明人： Akihito Iwai ,  Hiroshi Wada ,  Katsumi Matsumoto ,  Sosuke Naito ,  Yoshihiko Imai ,  Hideki Nakamura ,  Hiroaki Tanaka

IPC分类号： C04B35/10 ,  B02C13/28 ,  C04B35/119 ,  C04B35/48 ,  C04B35/488

CPC分类号： C04B35/4885 ,  B02C13/28 ,  C04B35/119

摘要： An alumina-zirconia sintered body comprising 92 to 35% by weight of aluminum oxide and 8 to 65% by weight of zirconium oxide having mainly tetragonal system, and 0.2 to 5 parts by weight of silicon oxide per 100 parts by weight of the total of aluminum oxide and zirconium oxide, and having a relative density of 95% or more, has improved wear resistance and suitable for use in an impact grinder.

公开(公告)号：US5280511A

公开(公告)日：1994-01-18

申请号：US940341

申请日：1992-09-03

申请人： Tatsuhisa Fujii ,  Iwao Takemoto ,  Atsushi Hasegawa ,  Kenji Kitajima ,  Tetsuro Izawa ,  Katsumi Matsumoto

发明人： Tatsuhisa Fujii ,  Iwao Takemoto ,  Atsushi Hasegawa ,  Kenji Kitajima ,  Tetsuro Izawa ,  Katsumi Matsumoto

IPC分类号： H03F3/50 ,  G11C19/28 ,  G11C27/04 ,  H03K5/02 ,  H04N5/14 ,  H04N5/335 ,  H04N5/341 ,  H04N5/369 ,  H04N5/372 ,  H04N5/374 ,  H04N5/378 ,  H03K3/353

CPC分类号： G11C19/285 ,  G11C27/04 ,  H03K5/023

摘要： Herein disclosed is an amplification circuit for realizing a substantially high sensitivity with a simple structure. The amplification circuit comprises: a first capacitor C1 for receiving a signal charge; a source-follower circuit for receiving a voltage of the first capacitor C1; an inversion amplification circuit including a source-earth type amplification MOSFET Q5 having its gate fed with the output signal of the source-follower circuit through a second capacitor C2; a feedback third capacitor C3 connected between the gate and drain of the amplification MOSFET Q5; and a switch element Q6 for feeding the gate of the amplification MOSFET Q5 with a predetermined bias voltage while the signal charge of the first capacitor C1 is being reset. The amplification MOSFET Q5 has its drain equipped as load means with a depletion type MOSFET Q4 having its gate and source connected, and the depletion type MOSFET Q4 has its source given the same potential as the substrate potential thereof.

摘要翻译： 这里公开了一种用简单结构实现基本上高灵敏度的放大电路。 放大电路包括：用于接收信号电荷的第一电容器C1; 用于接收第一电容器C1的电压的源极跟随器电路; 包括源极 - 放电型MOSFET Q5的反相放大电路，其栅极通过第二电容器C2馈送源极跟随器电路的输出信号; 连接在放大MOSFET Q5的栅极和漏极之间的反馈第三电容器C3; 以及开关元件Q6，用于在第一电容器C1的信号电荷被复位的同时以预定的偏置电压馈送放大MOSFET Q5的栅极。 放大MOSFET Q5的漏极配备为具有栅极和源极连接的耗尽型MOSFET Q4的负载装置，耗尽型MOSFET Q4的源极具有与其衬底电位相同的电位。

公开(公告)号：US5241667A

公开(公告)日：1993-08-31

申请号：US781176

申请日：1991-10-31

申请人： Katsumi Matsumoto

发明人： Katsumi Matsumoto

IPC分类号： G06F15/16 ,  G04G7/00 ,  G04G15/00 ,  G06F1/14 ,  G06F9/52 ,  G06F15/177

CPC分类号： G04G7/00 ,  G04G15/006

摘要： An apparatus connecting a main controller for controlling an operation of an electric equipment and a sub controller for conducting a clock operation through a communication device is characterized in that the main controller generates a data having a predetermined period based on a reference clock and sends out the data through the communication device, and in that the sub controller receives the data sent from the main controller through the communication device and conducts a clock operation based on the period of the data. Because clock information is produced based on a communication period of the data from the main controller, the sub controller does not need a highly precise reference oscillator.

公开(公告)号：US4847696A

公开(公告)日：1989-07-11

申请号：US77876

申请日：1987-07-27

申请人： Katsumi Matsumoto ,  Hideo Kunii ,  Hideki Yamamoto ,  Toshiyasu Mori

发明人： Katsumi Matsumoto ,  Hideo Kunii ,  Hideki Yamamoto ,  Toshiyasu Mori

IPC分类号： G04G15/00 ,  H04N5/782

CPC分类号： H04N5/782 ,  G04G15/006

摘要： A timer reservation display controller outputs data to be displayed on a display screen. The data includes a predetermined number of guidances, menus, and items associated with timer reservation for the recording of several weeks of TV programs. The data is displayed in complete week intervals beginning with the current day. In conjunction with the displayed data, a pointing device allows the user to point to and select the displayed data to choose desired timer reservation periods for TV programs recording.

摘要翻译： 定时预约显示控制器输出要显示在显示屏上的数据。 数据包括预定数量的指导，菜单和与用于记录数周电视节目的定时预约相关联的项目。 数据以当天开始的整周间隔显示。 结合显示的数据，指点设备允许用户指向并选择所显示的数据以选择用于电视节目录制的期望的定时预约期间。

公开(公告)号：US09134529B2

公开(公告)日：2015-09-15

申请号：US13553527

申请日：2012-07-19

申请人： Daisuke Sonoda ,  Jun Fujiyoshi ,  Kohei Takahashi ,  Takuo Kaitou ,  Katsumi Matsumoto

发明人： Daisuke Sonoda ,  Jun Fujiyoshi ,  Kohei Takahashi ,  Takuo Kaitou ,  Katsumi Matsumoto

IPC分类号： G09F13/04 ,  B05D5/06 ,  B44C1/22 ,  G02B5/22 ,  G02B26/02 ,  G09G3/34

CPC分类号： G02B26/02 ,  G09G3/3433 ,  G09G2300/0426 ,  G09G2300/08

摘要： A display device includes a substrate having an upper surface. The display device also includes a light reflecting layer to reflect light, formed over the upper surface of the substrate. The display device also includes a light absorbing layer to absorb light, formed over the upper surface of the light reflecting layer. A plurality of apertures are defined through the light reflecting layer and the light absorbing layer such that, at an edge of each of the plurality of apertures, the light absorbing layer partially overhangs the light reflecting layer.

摘要翻译： 显示装置包括具有上表面的基板。 显示装置还包括形成在基板的上表面上的反射光的光反射层。 显示装置还包括形成在光反射层的上表面上的吸收光的光吸收层。 通过光反射层和光吸收层限定多个孔，使得在多个孔中的每一个的边缘处，光吸收层部分地悬垂在光反射层上。

公开(公告)号：US08599462B2

公开(公告)日：2013-12-03

申请号：US13539708

申请日：2012-07-02

申请人： Takeomi Morita ,  Masataka Okamoto ,  Takahiko Muneyoshi ,  Shigeki Nishizawa ,  Katsumi Matsumoto

发明人： Takeomi Morita ,  Masataka Okamoto ,  Takahiko Muneyoshi ,  Shigeki Nishizawa ,  Katsumi Matsumoto

IPC分类号： G02B26/02 ,  G09G3/34

CPC分类号： G02F1/1336 ,  G02B26/02

摘要： A display device includes a first substrate; a second substrate; a plurality of pixels; a shutter mechanism section formed in correspondence with each of the pixels, a fluid sealed in an space between the first substrate and the second substrate; and an impact absorption section located to face one substrate among the first substrate and the second substrate, on the side opposite to the side on which the fluid is located. The shutter mechanism section is formed on the second substrate and includes a movable shutter section for controlling a light transmittance of each of the pixels. The impact absorption section includes a third substrate located to face the one substrate, on the side opposite to the fluid, a sealing section for bringing together the one substrate and the third substrate, and a predetermined gap formed among the one substrate, the third substrate and the sealing section.

摘要翻译： 显示装置包括第一基板; 第二基板; 多个像素; 与每个像素相对应地形成的快门机构部分，密封在第一基板和第二基板之间的空间中的流体; 以及冲击吸收部，其位于与所述第一基板和所述第二基板的面对一个基板的与所述流体所在的一侧相反的一侧。 快门机构部分形成在第二基板上，并且包括用于控制每个像素的透光率的可移动快门部分。 所述冲击吸收部包括位于与所述流体相反的一侧面对所述一个基板的第三基板，将所述一个基板和所述第三基板接合在一起的密封部以及在所述一个基板，所述第三基板 和密封部。

公开(公告)号：US08456401B2

公开(公告)日：2013-06-04

申请号：US12222339

申请日：2008-08-07

申请人： Katsumi Matsumoto ,  Kozo Yasuda ,  Yasukazu Kimura ,  Takuo Kaitoh ,  Toshihiko Itoga ,  Hiroshi Kageyama

发明人： Katsumi Matsumoto ,  Kozo Yasuda ,  Yasukazu Kimura ,  Takuo Kaitoh ,  Toshihiko Itoga ,  Hiroshi Kageyama

IPC分类号： G09G3/36 ,  H01L31/00 ,  H01L31/036

CPC分类号： H01L29/78618 ,  G02F1/13454 ,  G02F2001/13685 ,  G02F2202/104 ,  H01L27/12 ,  H01L29/78645 ,  H01L29/78696

摘要： The gate electrode is formed above the polycrystalline semiconductor layer through the gate insulating film. The polycrystalline semiconductor layer includes a first region overlapping with the gate electrode in plan view. The first region is sandwiched between the second region and the third region. The second region of the polycrystalline semiconductor layer includes a first impurity diffusion region and two second impurity diffusion regions opposite in conductivity type to the first impurity diffusion region. The first region and the first impurity diffusion region are in contact with each other at a first boundary. The first region and the two second impurity diffusion regions are in contact with each other at second boundaries. The two second impurity diffusion regions sandwiching the first impurity diffusion region are provided along the gate electrode. Thus, a leak current is suppressed.

公开(公告)号：US20120306562A1

公开(公告)日：2012-12-06

申请号：US13484034

申请日：2012-05-30

申请人： Mitsuhide Miyamoto ,  Katsumi Matsumoto ,  Takahide Kuranaga

发明人： Mitsuhide Miyamoto ,  Katsumi Matsumoto ,  Takahide Kuranaga

IPC分类号： H03K17/687

CPC分类号： G02B26/0841 ,  G09G3/346 ,  G09G2300/0417 ,  G09G2300/0857 ,  G09G2310/0262 ,  G11C23/00 ,  H03K3/0375

摘要： This disclosure provides novel latching circuits, and pixel circuits and display devices that include such latching circuits. The latches herein include a switch positioned on an inverter coupling interconnect which couples two cross-coupled inverters of the latch. The switch is configured to control a passage of a current between the first and second inverters. By switching the switch OFF at a time a data voltage is transferred to the inverters, any leak current between the inverters can be interrupted. As a result, a malfunctioning of the data latch is prevented.

摘要翻译： 本公开提供了新颖的锁存电路，以及包括这种锁存电路的像素电路和显示装置。 这里的锁存器包括位于反相器耦合互连上的开关，其耦合闩锁的两个交叉耦合的反相器。 开关被配置为控制第一和第二逆变器之间的电流通过。 通过将数据电压一次传送到逆变器，将开关切换到OFF状态，则可以中断逆变器之间的任何漏电流。 结果，防止了数据锁存器的故障。

公开(公告)号：US08203518B2

公开(公告)日：2012-06-19

申请号：US12392136

申请日：2009-02-25

申请人： Kozo Yasuda ,  Katsumi Matsumoto

发明人： Kozo Yasuda ,  Katsumi Matsumoto

IPC分类号： G09G3/36

CPC分类号： G09G3/20 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0289

摘要： Provided is a display device including a level shift circuit, which includes a thin film transistor having a polycrystalline semiconductor layer, and which realizes a reliable operation even when a threshold of the thin film transistor varies. The display device includes: a board; and the level shift circuit which includes the thin film transistor having the polycrystalline semiconductor layer, and is formed on the board, in which the level shift circuit includes: a plurality of source-input level shift circuits including a plurality of unit level shift circuits having drain resistors different in value from one another; and a selection circuit, which selects one of outputs from the plurality of unit level shift circuits as an output from a normally operated unit level shift circuit.

摘要翻译： 提供了一种包括电平移位电路的显示装置，其包括具有多晶半导体层的薄膜晶体管，并且即使当薄膜晶体管的阈值变化时也实现可靠的操作。 显示装置包括：板; 以及电平移位电路，其包括具有多晶半导体层的薄膜晶体管，并且形成在电路板上，其中电平移位电路包括：多个源极输入电平移位电路，包括多个单位电平移位电路，其具有 漏极电阻值彼此不同; 以及选择电路，其从所述多个单位电平移位电路中选择一个输出作为来自正常操作的单位电平移位电路的输出。

公开(公告)号：US07839373B2

公开(公告)日：2010-11-23

申请号：US12155357

申请日：2008-06-03

申请人： Kozo Yasuda ,  Katsumi Matsumoto

发明人： Kozo Yasuda ,  Katsumi Matsumoto

IPC分类号： G09G3/18

CPC分类号： G09G3/3655 ,  G09G2300/0809 ,  G09G2300/0823 ,  G09G2300/0857 ,  G09G2320/0257

摘要： A display device which arranges a memory part for every display pixel is configured to prevent a charge from remaining in liquid crystal when a power source is turned off. Each display pixel includes a memory part for storing video data, a pixel electrode, and a switch part for selectively applying a first video voltage or a second video voltage different from the first video voltage to the pixel electrode corresponding to the video data stored in the memory part. The display device further includes a reset circuit for allowing the first video voltage and the second video voltage to have the same voltage when a power source of the display device is turned off.

摘要翻译： 配置每个显示像素的存储部分的显示装置被配置为当电源关闭时防止电荷残留在液晶中。 每个显示像素包括用于存储视频数据的存储器部分，像素电极和开关部分，用于选择性地将与第一视频电压不同的第一视频电压或第二视频电压施加到与存储在视频数据中的视频数据相对应的像素电极 记忆部分。 显示装置还包括复位电路，用于当显示装置的电源关闭时允许第一视频电压和第二视频电压具有相同的电压。