公开(公告)号：US07105409B2

公开(公告)日：2006-09-12

申请号：US10899119

申请日：2004-07-27

申请人： Takashi Kobayashi ,  Yasushi Goto ,  Tokuo Kure ,  Hideaki Kurata ,  Hitoshi Kume ,  Katsutaka Kimura ,  Syunichi Saeki

发明人： Takashi Kobayashi ,  Yasushi Goto ,  Tokuo Kure ,  Hideaki Kurata ,  Hitoshi Kume ,  Katsutaka Kimura ,  Syunichi Saeki

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/7881

摘要： A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions 205 formed first conduction type well 201, floating gates 203b formed on semiconductor substrate 200 through an insulator film 202, control gates 211a formed on floating gates 203b through nitrogen-introduced silicon oxide film 210a and third gates 207a different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates 207a thus formed is made lower than that of floating gates 203b, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.

摘要翻译： 具有第三栅极的半导体集成电路器件包括形成在第一导电型阱201的第二导电型源极/漏极扩散层区域205，通过绝缘膜202形成在半导体衬底200上的浮置栅极203b，形成在浮动栅极203上的控制栅极211a b通过氮导入氧化硅膜210a和与通过半导体衬底，浮栅，控制栅极和绝缘膜形成的浮栅和控制栅极不同的第三栅极207a，其中第三栅极形成为 填充在垂直方向上存在的浮动栅极与字线和沟道之间的间隙以及如此形成的第三栅极207a的高度低于浮动栅极203b的高度，具有改善的存储单元尺寸和操作速度的降低和改进 编程/擦除周期后的可靠性。

公开(公告)号：US07092296B2

公开(公告)日：2006-08-15

申请号：US11138290

申请日：2005-05-27

申请人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

发明人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

IPC分类号： G11C16/04

CPC分类号： G11C16/0416 ,  G11C8/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

公开(公告)号：US20060172482A1

公开(公告)日：2006-08-03

申请号：US11393774

申请日：2006-03-31

申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L27/105 ,  G11C16/0416 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886

摘要： A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

公开(公告)号：US07071050B2

公开(公告)日：2006-07-04

申请号：US11220723

申请日：2005-09-08

申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

IPC分类号： H01L21/8238

CPC分类号： H01L27/105 ,  G11C16/0416 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886

摘要： A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

公开(公告)号：US06960501B2

公开(公告)日：2005-11-01

申请号：US10819205

申请日：2004-04-07

申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

IPC分类号： H01L21/8247 ,  H01L27/06 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L27/105 ,  G11C16/0416 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886

摘要： A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

摘要翻译： 一种具有非易失性存储单元的半导体存储器单元，每个非易失性存储单元分别由具有浮置栅极和控制栅极的MISFET形成，以及用作源极和漏极区域的第一和第二半导体区域。 根据其制造方法，引入杂质（例如砷）以形成第一和第二半导体区域，但是具有较低剂量的第二半导体区域，使得形成的第一半导体区域达到结深度 大于第二半导体区域，并且第一和第二半导体区域都具有在浮置栅电极下方延伸的部分。 该装置及其方法的特征还在于外围电路的MISFET的形成。

公开(公告)号：US06777282B2

公开(公告)日：2004-08-17

申请号：US10164626

申请日：2002-06-10

申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

IPC分类号： H01L218238

CPC分类号： H01L27/105 ,  G11C16/0416 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886

摘要： A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

摘要翻译： 一种具有非易失性存储单元的半导体存储器单元，每个非易失性存储单元分别由具有浮置栅极和控制栅极的MISFET形成，以及用作源极和漏极区域的第一和第二半导体区域。 根据其制造方法，引入杂质（例如砷）以形成第一和第二半导体区域，但是具有较低剂量的第二半导体区域，使得形成的第一半导体区域达到结深度 大于第二半导体区域，并且第一和第二半导体区域都具有在浮置栅电极下方延伸的部分。 该装置及其方法的特征还在于外围电路的MISFET的形成。

公开(公告)号：US06438028B1

公开(公告)日：2002-08-20

申请号：US09616072

申请日：2000-07-13

申请人： Takashi Kobayashi ,  Hideaki Kurata ,  Naoki Kobayashi ,  Hitoshi Kume ,  Katsutaka Kimura ,  Shunichi Saeki

发明人： Takashi Kobayashi ,  Hideaki Kurata ,  Naoki Kobayashi ,  Hitoshi Kume ,  Katsutaka Kimura ,  Shunichi Saeki

IPC分类号： G11C700

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115

摘要： In a semiconductor integrated circuit device including a third gate, the present invention improves miniaturization and operation speed and reduces a defect density of an insulator film. In a semiconductor integrated circuit device including a well of a first conductivity type formed in a semiconductor substrate, a source/drain diffusion layer of a second conductivity type inside the well, a floating gate formed over the semiconductor substrate through an insulator film, a control gate formed and isolated from the floating gate through an insulator film, word lines formed by connecting the control gates and a third gate formed and isolated from the semiconductor substrate, the floating gate and the control gate through an insulator film and different from the floating gate and the control gate, the third gate is buried into a space of the floating gates existing in a direction vertical to the word line and a channel.

摘要翻译： 在包括第三栅极的半导体集成电路器件中，本发明改进了小型化和操作速度并降低了绝缘膜的缺陷密度。 在包括形成在半导体衬底中的第一导电类型阱的阱的半导体集成电路器件中，阱内部具有第二导电类型的源极/漏极扩散层，通过绝缘膜形成在半导体衬底上的浮置栅极， 栅极通过绝缘体膜从浮栅形成并隔离，通过连接控制栅极和通过绝缘膜形成并与半导体衬底，浮栅和控制栅极隔离的第三栅极形成的字线并且不同于浮置栅极 并且控制栅极，第三栅极被埋在垂直于字线和通道的方向上存在的浮动栅极的空间中。

公开(公告)号：US06255690B1

公开(公告)日：2001-07-03

申请号：US09282204

申请日：1999-03-31

申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

IPC分类号： H01L29788

CPC分类号： H01L27/105 ,  G11C16/0416 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886

摘要： A semiconductor memory device having nonvolatile memory cells of a single-element type. The nonvolatile memory cells have a floating gate electrode insulatedly on a main surface of a semiconductor substrate and a control gate electrode on the floating gate via a second gate insulating film. An impurity, for example, arsenic, is introduced in self-alignment with the pair of opposing end sides of the control gate electrode to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. In accordance with the scheme, the first semiconductor region is formed to have a junction depth greater than the junction depth associated with the second semiconductor region and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. Moreover, carriers which are stored in the floating gate electrode are transferred therefrom to the first semiconductor region by tunneling through the insulating film beneath the floating gate electrode.

摘要翻译： 一种具有单一元件类型的非易失性存储单元的半导体存储器件。 非易失性存储单元通过第二栅极绝缘膜，在半导体衬底的主表面和浮动栅极上的控制栅电极上绝缘地具有浮栅电极。 引入与控制栅电极的一对相对端侧自对准的杂质，以形成第一和第二半导体区域，然而，较低剂量的砷被引入到 第二半导体区域。 根据该方案，第一半导体区域形成为具有大于与第二半导体区域相关联的结深度的结深度，并且第一和第二半导体区域都具有在浮置栅极下方延伸的部分。 此外，存储在浮栅电极中的载流子通过隧穿穿过浮置栅电极下方的绝缘膜而从其转移到第一半导体区域。

公开(公告)号：US06201735B1

公开(公告)日：2001-03-13

申请号：US09362719

申请日：1999-07-29

申请人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

发明人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

IPC分类号： G11C1604

CPC分类号： G11C16/0416 ,  G11C8/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： Each memory cell of a nonvolatile semiconductor memory, essentially, consists of a one-transistor type memory cell such as a MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Furthermore, because the negative voltage is applied to the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.

摘要翻译： 非易失性半导体存储器的每个存储单元基本上由诸如具有浮置栅电极的MOSFET的单晶体管型存储单元组成。 当执行电编程操作时，向n型漏极区域施加正电压，向控制栅极施加负电压，并且源极区域接地。 当执行擦除操作时，正电压被施加到控制栅极，而所有其它电极和半导体衬底接地。 可以实现低功耗，因为通过利用隧道机制来执行编程操作和擦除操作两者。 此外，因为负电压被施加到字线，所以可以降低编程数据时的漏极电压，从而可以减轻沟道部分处的栅极氧化膜的劣化。

公开(公告)号：US6157576A

公开(公告)日：2000-12-05

申请号：US393301

申请日：1999-09-10

申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

摘要翻译： 在具有其中电可擦除非易失性存储元件以矩阵形式布置的存储器阵列的EEPROM中，包括擦除控制电路，其在执行擦除操作之后在对应的存储器单元上至少执行一次读出操作 根据外部提供的擦除操作指令。 擦除操作由内部擦除控制电路自动执行，同时响应于来自微处理器的指令，EEPROM与微处理器电隔离。 微处理器的控制只需要稍微短的时间段，在擦除操作期间EEPROM保留在系统中时，指令擦除开始。 在本发明的一个方面中，将Vcc电源施加到每个非易失性半导体存储单元的源极区域或漏极区域，并且将具有与Vcc电源的极性相反的极性的擦除电压施加到控制栅极 电极。 擦除电压被提供给设置在非易失性存储器件内的电压转换电路。 因此，可以通过Vcc单电源实现擦除操作。 此外，响应于每个存储元件的单独擦除速度，对于每个存储元件或每个集合存储元件单独控制集体擦除操作的实质端子。