公开(公告)号：US20190245038A1

公开(公告)日：2019-08-08

申请号：US15913533

申请日：2018-03-06

Applicant: United Microelectronics Corp.

Inventor： Shin-Hung Li ,  Kuan-Chuan Chen ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/08 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L21/76224 ,  H01L27/0617 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor device includes semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

公开(公告)号：US10084083B1

公开(公告)日：2018-09-25

申请号：US15785606

申请日：2017-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li ,  Kuan-Chuan Chen ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/36 ,  H01L29/06 ,  H01L27/02 ,  G03F1/36 ,  H01L21/308 ,  H01L21/265 ,  H01L21/762 ,  H01L21/324 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7833 ,  G03F1/36 ,  H01L21/26513 ,  H01L21/3086 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/42372 ,  H01L29/66575 ,  H01L29/7836

Abstract: A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.

公开(公告)号：US20170207127A1

公开(公告)日：2017-07-20

申请号：US15475097

申请日：2017-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li ,  Kuan-Chuan Chen ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/31051 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.