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51.发明授权
公开(公告)号：US5754134A
公开(公告)日：1998-05-19
申请号：US534869
申请日：1995-09-27
摘要： An A/D converter including a first inverter having a linear characteristic and receiving an analog input voltage, a first quantizing circuit for quantizing the analog input voltage, a capacitive coupling to which an output of the first inverter and the first quantizing circuit are inputted, a second inverter receiving an output of the capacitive coupling and having the same characteristic of the first inverter, and a second quantizing circuit for receiving and quantizing an output of the second inverter. The A/D converter performs successive steps of quantizing/digitizing so as to achieve A/D conversion.
摘要翻译： 一种A / D转换器，包括具有线性特征并接收模拟输入电压的第一反相器，用于量化模拟输入电压的第一量化电路，输入第一反相器和第一量化电路的输出的电容耦合， 接收所述电容耦合的输出并具有与所述第一反相器相同的特性的第二反相器，以及用于接收和量化所述第二反相器的输出的第二量化电路。 A / D转换器执行量化/数字化的连续步骤，以实现A / D转换。
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公开(公告)号：US5754133A
公开(公告)日：1998-05-19
申请号：US513657
申请日：1995-08-11
申请人： Guoliang Shou , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Makoto Yamamoto , Sunao Takatori
摘要： A register circuit for holding an analog input voltage includes a plurality of thresholding circuits of stepwise thresholds, an integrating circuit for integrating outputs of the thresholding circuits and a switching circuit for alternatively inputting an output of the integrating circuit or the analog input voltage to the thresholding circuits as the input voltage of the capacitive coupling.
摘要翻译： 用于保持模拟输入电压的寄存器电路包括多个阶跃阈值阈值电路，用于积分阈值电路的输出的积分电路和用于交替地将积分电路的输出或模拟输入电压输入到阈值的开关电路 电路作为电容耦合的输入电压。
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公开(公告)号：US5686861A
公开(公告)日：1997-11-11
申请号：US630505
申请日：1996-04-10
申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
CPC分类号： H03H11/04
摘要： A filter circuit that consumes very little electric power. The active filter is a linear inverter constructed by 1) an inverting amplifying portion composed of an odd number of MOS inverters serially connected, 2) a grounded capacitance connected between an output of the inverting amplifying portion and ground, 3) a balancing resistance having a pair of resistances for connecting an output of one of the MOS inverters, other than the last MOS inverter, to the supply voltage and the ground, respectively, and 4) a feedback impedance for connecting the output and input of the inverting amplifying portion. A coupling capacitance is connected to the input of the linear inverter and a plurality of filter circuits are connected to an input of the coupling capacitance.
摘要翻译： 一种消耗很少电力的滤波电路。 有源滤波器是一种线性反相器，由1）由串联连接的奇数个MOS反相器组成的反相放大部分，2）连接在反相放大部分的输出端和地之间的接地电容，3）平衡电阻，具有 一对电阻分别用于将MOS逆变器之一以外的输出连接到电源电压和接地，以及4）用于连接反相放大部分的输出和输入的反馈阻抗。 耦合电容连接到线性反相器的输入，并且多个滤波电路连接到耦合电容的输入。
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公开(公告)号：US5650752A
公开(公告)日：1997-07-22
申请号：US458179
申请日：1995-06-02
申请人： Guoliang Shou , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Makoto Yamamoto , Sunao Takatori
摘要： An amplifier circuit has a wide frequency range which is broader than the frequency range expected from its circuit parameters. The amplifier circuit comprises a plurality of unit amplifier circuits connected in parallel. Each unit amplifier circuit contains an odd number of inverters serially connected from the first stage to the last stage, an input capacitance connected to the input terminal of the first stage, and a feedback capacitance connecting the output terminal of the inverter of the last stage to the input terminal of the inverter of the first stage. Thus, the amplifier circuit operates in a wide frequency range with little decrease in gain at high frequencies.
摘要翻译： 放大器电路具有比从其电路参数预期的频率范围宽的宽的频率范围。 放大器电路包括并联连接的多个单元放大器电路。 每个单位放大器电路包括从第一级到最后级串联连接的奇数个反相器，连接到第一级的输入端的输入电容和将最后级的反相器的输出端连接到 第一级逆变器的输入端。 因此，放大器电路在宽频率范围内工作，在高频下的增益几乎没有降低。
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55.发明授权High-speed circuit for performing pattern matching of image data and the like suitable for large scale integration implementation 失效用于执行适合于大规模集成实现的图像数据等的图案匹配的高速电路
公开(公告)号：US5579411A
公开(公告)日：1996-11-26
申请号：US426587
申请日：1995-04-21
申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
CPC分类号： G06K9/6202 , G06F17/153
摘要： A pattern matching system includes a circuit that matches an input image with a template based on a correlation function. The circuit has a structure which makes it particularly suitable for implementation in Large Scale Integration (LSI) technologies. A pattern matching circuit according to this invention sets up a threshold value of a correlation coefficient and evaluates the following formula,E=N.sup.2 {.SIGMA.(f.sub.i -f.sub.m) (g.sub.i -g.sub.m)}.sup.2 -p.sub.th.sup.2 N.sup.2 .sigma..sub.f.sup.2 .sigma..sub.g.sup.2where N is a number of input data points. f.sub.1 is an input data point. f.sub.m is a mean value of input data points. g.sub.1 is a template data point. g.sub.m is a mean value of template data points. .sigma..sub.f is a standard deviation of input data points and .sigma..sub.g is a standard deviation of template data points in a range over a threshold value.
摘要翻译： 模式匹配系统包括基于相关函数将输入图像与模板匹配的电路。 该电路具有特别适用于大规模集成（LSI）技术实现的结构。 根据本发明的模式匹配电路建立相关系数的阈值，并且评估下列公式：E = N2 {SIGMA（fi-fm）（gi-gm）} 2-pth2N2 sigma f2 sigma g2其中N是 输入数据点数。 f1是输入数据点。 fm是输入数据点的平均值。 g1是模板数据点。 gm是模板数据点的平均值。 西格玛f是输入数据点的标准偏差，σg是在超过阈值的范围内的模板数据点的标准偏差。
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公开(公告)号：US5467376A
公开(公告)日：1995-11-14
申请号：US308460
申请日：1994-09-19
申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
CPC分类号： G06F7/5055
摘要： A counter circuit converts a full count to a zero count and a zero count to a full count. An incrementing counter circuit according to the present invention has a plurality of threshold circuits with stepwise thresholds. An output of the highest threshold circuit is used as a cut off signal for other threshold circuits. A decrementing counter circuit according to the present invention has a plurality of threshold circuits from the lowest threshold to the highest thresholds. An output of the lowest threshold circuit is used as a closing signal for other threshold circuits.
摘要翻译： 计数器电路将完全计数转换为零计数，将零计数转换为完全计数。 根据本发明的递增计数器电路具有多个具有逐步阈值的阈值电路。 最高阈值电路的输出用作其他阈值电路的截止信号。 根据本发明的递减计数器电路具有从最低阈值到最高阈值的多个阈值电路。 最低阈值电路的输出用作其他阈值电路的闭合信号。
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公开(公告)号：US5394107A
公开(公告)日：1995-02-28
申请号：US111870
申请日：1993-08-26
申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
摘要： An absolute value circuit for analog type processing combines an analog inverter circuit and a maximum circuit. The inverter circuit uses an operational amplifier comprised of CMOS inverters which are connected in a cascade with a gain of 1. The maximum circuit includes a pair of nMOS transistors, the source follower outputs of which are connected to a common output.
摘要翻译： 用于模拟型处理的绝对值电路组合了模拟逆变器电路和最大电路。 逆变器电路使用由CMOS反相器组成的运算放大器，其以1的增益级联连接。最大电路包括一对nMOS晶体管，其源极跟随器输出端连接到公共输出端。
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58.发明授权Image compressing method compressing an image into a compressed image and error coefficients 失效图像压缩方法将图像压缩成压缩图像和误差系数
公开(公告)号：US5363205A
公开(公告)日：1994-11-08
申请号：US105058
申请日：1993-08-12
申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
IPC分类号： H03M7/30 , H04N1/41 , H04N1/411 , H04N7/14 , H04N7/18 , H04N7/26 , H04N1/415 , H04N1/417 , H04N7/13
CPC分类号： H04N19/63
摘要： An image compression method which successively diminishes in size the image to form a compressed image. The compression is done by dividing an image into partial areas with equal size, calculating a mean pixel value in each area, and substituting the mean pixel value into the diminished image. The image is then re-enlarged in the same way, and the enlarged image is compared against the original image to determine error values. The error values and the diminished images are used to represent a compressed version of the original image.
摘要翻译： 图像压缩方法，其连续地缩小图像以形成压缩图像。 通过将图像划分为相同尺寸的部分区域来进行压缩，计算每个区域中的平均像素值，并将平均像素值代入缩小的图像。 然后以相同的方式重新放大图像，并将放大的图像与原始图像进行比较以确定误差值。 错误值和减少的图像用于表示原始图像的压缩版本。
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59.发明授权Matched filter for spread spectrum communication systems and hybrid analog-digital transversal filter 失效用于扩频通信系统和混合模数转换滤波器的匹配滤波器公开(公告)号：US06169771A
公开(公告)日：2001-01-02
申请号：US09014264
申请日：1998-01-27
申请人： Guoliang Shou , Changming Zhou , Xuping Zhou , Xiaoling Oin , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Changming Zhou , Xuping Zhou , Xiaoling Oin , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
IPC分类号： H04L2706
CPC分类号： H03H17/0254 , H04B1/7093
摘要： In one aspect, the present invention provides a low power consumption matched filter. The signal received at an input terminal is input to a shift register having stages equal to the spread code length number after conversion into digital signals in an A/D converter. The outputs of the shift register stages are input to XOR circuits set corresponding to each stage, so that XOR operations are performed between the outputs and corresponding spread code bits d1 to dN. The outputs of the XOR circuits are analogously added in an analog adder and output from an output terminal. In another aspect, a filter circuit uses an analog operation circuit to prevent lowered operational accuracy caused by residual charge. Input analog signals successively undergo sampling and holding in sample-and-hold circuits, are multiplied by coefficients stored in a shift register by multiplication circuits, and added in an addition circuit. Sample data transmission error storage is prevented by shifting coefficients in the shift register. Sample-and-hold circuits and multiplication circuits are formed by analog operation circuits, and each include a switch for canceling the residual charge. The sample-and-hold circuits and multiplication circuits normally working are refreshed sequentially by providing circuits for replacing their function. The addition circuit is refreshed in the same way.
摘要翻译： 一方面，本发明提供一种低功耗匹配滤波器。 在A / D转换器转换成数字信号之后，在输入端接收的信号被输入到具有等于扩展码长度数的级的移位寄存器。 移位寄存器级的输出被输入到对应于每一级的XOR电路，从而在输出和对应的扩展码位d1至dN之间执行异或运算。 XOR电路的输出类似地添加到模拟加法器中并从输出端子输出。 另一方面，滤波器电路使用模拟运算电路来防止由剩余电荷引起的运算精度降低。 输入模拟信号在采样保持电路中连续进行采样和保持，乘以乘法电路存储在移位寄存器中的系数，并加入加法电路。 通过移位寄存器中的系数来防止采样数据传输错误存储。 采样保持电路和乘法电路由模拟操作电路形成，并且每个都包括用于消除剩余电荷的开关。 正常工作的采样保持电路和乘法电路通过提供更换其功能的电路依次刷新。 加法电路以相同的方式刷新。
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公开(公告)号：US06031415A
公开(公告)日：2000-02-29
申请号：US733820
申请日：1996-10-18
申请人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Mamoru Sawahashi , Fumiyuki Adachi , Sunao Takatori
发明人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Mamoru Sawahashi , Fumiyuki Adachi , Sunao Takatori
IPC分类号： H04J13/00 , H03H17/02 , H04B1/7093 , H03K5/00 , H03D1/00
CPC分类号： H03H17/0254 , H04B1/707
摘要： The present invention provides a matched filter circuit available for processing long P/N codes in a small size circuit. A matched filter circuit according to the present invention performs the following processes in the proposed invention: i) sampling and holding circuits multiply part of the number of a long code; ii) multipliers are input in parallel to the sampling and holding circuit from the first multiplier register which can hold as many PN codes as the number of the sampling and holding circuits in i); iii) the PN codes are stored in the second multiplier register of the same capacity of the first multiplier resister when there is a PN code to be used sequentially to be PN codes; and iv) the PN codes in the second multiplier register are transmitted in parallel to the first multiplier register. The PN code is input to the second multiplier register in serial.
摘要翻译： 本发明提供了可用于处理小尺寸电路中的长P / N码的匹配滤波器电路。 根据本发明的匹配滤波器电路在所提出的发明中执行以下处理：i）采样和保持电路乘以长码的数量的一部分; ii）乘法器与来自第一乘法器寄存器的采样和保持电路并联输入，其可以容纳与i）中的采样和保持电路的数量一样多的PN码; iii）当存在要被顺序使用的PN码为PN码时，PN码存储在第一乘法器电阻相同容量的第二乘法器寄存器中; 和iv）第二乘法器寄存器中的PN码并行发送到第一乘法器寄存器。 PN码以串行方式输入到第二个乘法器寄存器。
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