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公开(公告)号：US12198036B2
公开(公告)日：2025-01-14
申请号：US17324062
申请日：2021-05-18
Applicant: Winbond Electronics Corp.
Inventor： Yasuhiro Tomita , Masaru Yano
Abstract: A resistance variable type synapse array apparatus that can perform STDP writing using a positive potential is provided. The synapse array apparatus includes a writing unit writing to a selected resistance variable type memory element in a crossbar array. The writing unit includes a driver generating a positive pulse signal corresponding to a positive part of a spike signal generated by a presynaptic neuron, a driver generating a positive pulse signal corresponding to a negative part of a spike signal generated by a postsynaptic neuron, a driver generating a positive pulse signal corresponding to a positive part of the spike signal generated by the postsynaptic neuron, and a driver generating a positive pulse signal corresponding to a negative part of the spike signal generated by the presynaptic neuron.
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公开(公告)号：US11978515B2
公开(公告)日：2024-05-07
申请号：US17179409
申请日：2021-02-19
Applicant: Winbond Electronics Corp.
Inventor： Riichiro Shirota , Masaru Yano
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/10
Abstract: A semiconductor memory device capable of reducing failure caused by a source side effect after a large number of W/E cycles is provided. A reading method of a NAND flash memory includes: dividing multiple word lines connected to each memory cell of a NAND string into a group 1 of word lines WL0 to WLi−1, a group 2 of word lines WLi to WLj, . . . , a group y of word lines WLj+1 to WLk−1, and a group x of word lines WLk to WLn, presetting a relationship that each readout voltage (Vread1, Vread2, . . . , Vready, and Vreadx) corresponding to each group increases toward a bit line side, and applying a readout voltage to a selected word line according to the relationship.
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公开(公告)号：US20230386574A1
公开(公告)日：2023-11-30
申请号：US18321791
申请日：2023-05-23
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
CPC classification number: G11C16/0433 , G11C16/102 , G11C16/14
Abstract: A flash memory capable of achieving high integration and low power consumption is formed by an AND-type memory cell array, an address buffer, a row selecting/driving circuit, a column selecting circuit, an input and output circuit, and a read/write control part. A memory cell includes, for example, a charge storage layer of an ONO structure. The read/write control part performs programming and erasing by Fowler-Nordheim (FN) tunneling between the charge storage layer and a channel of a selected memory cell.
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公开(公告)号：US20230186997A1
公开(公告)日：2023-06-15
申请号：US17988782
申请日：2022-11-17
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano , Toshiaki Takeshita
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/3445
Abstract: The disclosure provides a semiconductor device and an erasing method that may alleviate the deterioration of a memory cell caused by ISPE. The NAND flash memory in the disclosure includes a memory cell array and an erasing component that erases selected blocks of the memory cell array. The erasing component performs a first erasing verification (EV1) and a second erasing verification (EV2) on the selected block. When the first erasing verification (EV1) passes, and the second erasing verification (EV2) fails, an erase pulse with the same erase voltage as the last time is applied, and when the first erasing verification (EV1) fails, an erase pulse with a step voltage higher than the last time is applied.
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公开(公告)号：US11594279B2
公开(公告)日：2023-02-28
申请号：US17367651
申请日：2021-07-06
Applicant: Winbond Electronics Corp.
Inventor： Yasuhiro Tomita , Masaru Yano
Abstract: An array device and a writing method thereof are provided. A synapse array device includes: a crossbar array, in which a resistive memory element is connected to each intersection of a plurality of row lines and a plurality of column lines; a row select/drive circuit selecting a row line of the crossbar array and applying a pulse signal to the selected row line; a column select/drive circuit selecting a column line of the crossbar array and applying a pulse signal to the selected column line; and a writing part writing to the resistive memory element connected to the selected row line and the selected column line. A first write voltage with controlled pulse width is applied to the selected row line, and a second write voltage with controlled pulse width is applied to the selected column line to perform set writing of the resistive memory element.
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Patent Agency Ranking
公开(公告)号：US20220406353A1
公开(公告)日：2022-12-22
申请号：US17736995
申请日：2022-05-04
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
IPC: G11C11/00
Abstract: A semiconductor storage device and its writing method are provided. A memory cell array is formed on a substrate, and the memory cell array has an NOR array with an NOR flash memory structure and a resistive random access array with a resistive random access memory (RRAM) structure. A read/write control unit charges a selected global bit line when a set write operation is performed on a selected memory cell of the resistive random access array, and a set write voltage is applied to the selected memory cell by applying a voltage charging the selected global bit line.
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公开(公告)号：US20220383919A1
公开(公告)日：2022-12-01
申请号：US17727834
申请日：2022-04-25
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
Abstract: A semiconductor storage device capable of achieving low power and high integration is provided. A non-volatile semiconductor memory of the disclosure includes a memory cell array. The memory cell array has a NOR array with a NOR flash memory structure and a variable resistance array with a variable resistance memory structure formed on a substrate. An entry gate is formed between the NOR array and the variable resistance array. When the NOR array is accessed, the entry gate separates the variable resistance array from the NOR array.
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公开(公告)号：US20220068393A1
公开(公告)日：2022-03-03
申请号：US17462006
申请日：2021-08-31
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano , Toshiaki Takeshita
Abstract: A semiconductor storage apparatus programming a memory cell through improved ISPP is introduced. A NAND flash memory programming method includes a step of selecting a page of a memory cell array and applying a programming pulse based on the ISPP to the selected page. The programming pulse applied by the ISPP includes a sacrificial programming pulse for which a program verification becomes unqualified due to an initial programming pulse and a last programming pulse having an increment larger than any increment of other programming pulses.
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公开(公告)号：US11100983B2
公开(公告)日：2021-08-24
申请号：US16860022
申请日：2020-04-27
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
Abstract: An electron device using a crossbar array and capable of implementing a high-speed and high-reliability process is provided. An operational processing device (100) includes a crossbar array (110); a row selecting/driving circuit (120) electrically coupling to a row line; a column selecting/driving circuit (130) electrically coupling to a column line; and a control part (140) controlling each part. The control part (140) is capable of applying, from the row selecting/driving circuit (120), an output signal received by the row selecting/driving circuit (120) or applying, from the column selecting/driving circuit (130), an output signal received by the column selecting/driving circuit (130).
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公开(公告)号：US11075770B2
公开(公告)日：2021-07-27
申请号：US16725345
申请日：2019-12-23
Applicant: Winbond Electronics Corp.
Inventor： Masaru Yano
Abstract: A semiconductor device is provided. The semiconductor device includes a unique-information generation portion, a detection portion, a memory portion, and a readout portion. The unique-information generation portion operates in a plurality of operation environments to generate unique information. The unique information includes stable information and unstable information. The stable information is constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments. The detection portion detects the unstable information. The memory portion stores the unique information and identification information for identifying the unstable information. The readout portion reads out the unique information and the identification information and outputs the unique information and the identification information to an external portion.
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