公开(公告)号：US20120257443A1

公开(公告)日：2012-10-11

申请号：US13528025

申请日：2012-06-20

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： G11C11/40

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

摘要翻译： 在最新的工艺中，栅极隧道泄漏电流增加，因此需要减小由用于蜂窝电话的电池驱动的LSI中的栅极隧道泄漏电流，并且需要在 待机模式处于低漏电流。 在半导体集成电路器件中，逻辑和存储电路的接地源电极线保持在有源模式的接地电位，并且在未选择待机模式下保持在比地电位高的电压。 可以减少栅极漏电流而不破坏数据。

公开(公告)号：US08232589B2

公开(公告)日：2012-07-31

申请号：US13352142

申请日：2012-01-17

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： H01L29/788 ,  H01L21/8242

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

摘要翻译： 在最新的工艺中，栅极隧道泄漏电流增加，因此需要减小由用于蜂窝电话的电池驱动的LSI中的栅极隧道泄漏电流，并且需要在 待机模式处于低漏电流。 在半导体集成电路器件中，逻辑和存储电路的接地源电极线保持在有源模式的接地电位，并且在未选择待机模式下保持在比地电位高的电压。 可以减少栅极漏电流而不破坏数据。

公开(公告)号：US20120113709A1

公开(公告)日：2012-05-10

申请号：US13352142

申请日：2012-01-17

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： G11C11/40

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

摘要翻译： 在最新的工艺中，栅极隧道泄漏电流增加，因此需要减小由用于蜂窝电话的电池驱动的LSI中的栅极隧道泄漏电流，并且需要在 待机模式处于低漏电流。 在半导体集成电路器件中，逻辑和存储电路的接地源电极线保持在有源模式的接地电位，并且在未选择待机模式下保持在比地电位高的电压。 可以减少栅极漏电流而不破坏数据。

公开(公告)号：US08125017B2

公开(公告)日：2012-02-28

申请号：US13067177

申请日：2011-05-13

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： H01L29/788 ,  H01L21/8242

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

公开(公告)号：US20110021022A1

公开(公告)日：2011-01-27

申请号：US12896933

申请日：2010-10-04

申请人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

发明人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

IPC分类号： H01L21/768

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.

摘要翻译： 在形成五个埋入中间导电层的沟槽中，用于连接转移MISFET和驱动MISFET与其上形成的垂直MISFET，其中第二和第三沟槽以及第一，第四和第五沟槽分别通过使用第一和第二 光刻胶膜作为掩模。 由于即使在第一沟槽和第二或第三沟槽之间的最短距离以及第二沟槽和第三沟槽与第四沟槽之间的最短距离小于分辨率极限的情况下，也可以以高精度形成所有沟槽 对于曝光光，布置在一个相同存储单元中的五个沟槽中的每一个之间的距离可以减小到小于曝光光的分辨率极限。

公开(公告)号：US20100136778A1

公开(公告)日：2010-06-03

申请号：US12700344

申请日：2010-02-04

申请人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

发明人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC分类号： H01L21/28

CPC分类号： H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

摘要翻译： 垂直MISFET形成在驱动MISFET和传输MISFET上。 垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极 插入其间。 在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。 下半导体层，中间半导体层和上半导体层均由硅膜构成。 下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

公开(公告)号：US20090275193A1

公开(公告)日：2009-11-05

申请号：US12435446

申请日：2009-05-05

申请人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

发明人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

IPC分类号： H01L21/768

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.

摘要翻译： 在形成五个埋入中间导电层的沟槽中，用于连接转移MISFET和驱动MISFET与其上形成的垂直MISFET，其中第二和第三沟槽以及第一，第四和第五沟槽分别通过使用第一和第二 光刻胶膜作为掩模。 由于即使在第一沟槽和第二或第三沟槽之间的最短距离以及第二沟槽和第三沟槽与第四沟槽之间的最短距离小于分辨率极限的情况下，也可以以高精度形成所有沟槽 对于曝光光，布置在一个相同存储单元中的五个沟槽中的每一个之间的距离可以减小到小于曝光光的分辨率极限。

公开(公告)号：US07582950B2

公开(公告)日：2009-09-01

申请号：US11190011

申请日：2005-07-27

申请人： Kazuhito Matsukawa ,  Tsuyoshi Koga ,  Akio Nishida ,  Yoshiko Higashide ,  Jun Shibata ,  Hiroshi Tobimatsu

发明人： Kazuhito Matsukawa ,  Tsuyoshi Koga ,  Akio Nishida ,  Yoshiko Higashide ,  Jun Shibata ,  Hiroshi Tobimatsu

IPC分类号： H01L29/06

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 μm or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

摘要翻译： 在半导体芯片A中，其中在正面上形成具有晶体管等的元件层2，并且背面与诸如封装基板的底层部件接合，厚度T为100μm以下， 此后，在半导体芯片A的背面上形成吸气层3.吸气层3例如通过使用研磨机对所述半导体芯片A的背面进行研磨而形成。 因此，在组装包装的步骤中可以提高装置的产量。

公开(公告)号：US20080268639A1

公开(公告)日：2008-10-30

申请号：US12146599

申请日：2008-06-26

申请人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

发明人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.

摘要翻译： 在形成五个埋入中间导电层的沟槽中，用于连接转移MISFET和驱动MISFET与其上形成的垂直MISFET，其中第二和第三沟槽以及第一，第四和第五沟槽分别通过使用第一和第二 光刻胶膜作为掩模。 由于即使在第一沟槽和第二或第三沟槽之间的最短距离以及第二沟槽和第三沟槽与第四沟槽之间的最短距离小于分辨率极限的情况下，也可以以高精度形成所有沟槽 对于曝光光，布置在一个相同存储单元中的五个沟槽中的每一个之间的距离可以减小到小于曝光光的分辨率极限。

公开(公告)号：US07433208B2

公开(公告)日：2008-10-07

申请号：US10564025

申请日：2005-04-20

申请人： Akio Nishida ,  Fumi Kitao ,  Hiroshi Takemura

发明人： Akio Nishida ,  Fumi Kitao ,  Hiroshi Takemura

IPC分类号： H02M3/335

CPC分类号： H02M3/3381

摘要： A switching power supply device includes a primary winding of a transformer that is connected in series to a first switching element, and a secondary winding is provided with a rectifier circuit and an output voltage control circuit arranged to detect an output voltage and feed it back to a control circuit. The control circuit is provided with an on-period control circuit arranged to turn off the first switching element in an on-state based on a feedback signal from the output voltage control circuit and an off-period control circuit arranged to control an off-period thereof by delaying turn-on of the first switching element based on the feedback signal.

摘要翻译： 开关电源装置包括与第一开关元件串联连接的变压器的初级绕组，次级绕组设置有整流电路和输出电压控制电路，其布置成检测输出电压并将其馈送回 一个控制电路。 所述控制电路设置有接通时间控制电路，其布置成基于来自所述输出电压控制电路的反馈信号而将所述第一开关元件断开，并且将所述第一开关元件设置为断开时段控制电路， 其基于反馈信号延迟第一开关元件的导通。