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122 条记录 (耗时 0.034 秒)

    Controller, data storage device and program product
    52.
    发明授权
    Controller, data storage device and program product 有权
    控制器，数据存储设备和程序产品

    公开(公告)号：US08533560B2

    公开(公告)日：2013-09-10

    申请号：US13218812

    申请日：2011-08-26

    申请人： Kazuhiro Fukutomi ,  Shinichi Kanno ,  Shigehiro Asano

    发明人： Kazuhiro Fukutomi ,  Shinichi Kanno ,  Shigehiro Asano

    IPC分类号： H03M13/00

    CPC分类号： G06F11/1048

    摘要： According to an embodiment of a controller, a bit string manipulating unit manipulates a bit string of manipulation target data based on a predetermined rule. A special data setting unit generates a magic number based on a special data setting request from a host interface, obtains an error detecting code for the magic number, and sends the magic number and the error detecting code as manipulation target data to the bit string manipulating unit to obtain a manipulated manipulation target data. The special data setting unit also extracts logical block address information from the special data setting request, and instructs an access unit to write the magic number in the manipulated manipulation target data to a user data storage area and to write the error detecting code in the manipulated manipulation target data to a redundant area in a storage area located by the logical block address information.

    摘要翻译： 根据控制器的实施例，位串操作单元基于预定规则来操纵操作对象数据的位串。 专用数据设定部基于来自主机接口的特殊数据设定请求生成魔术数，获得魔术数的错误检测码，将魔术号码和错误检测码作为操作对象数据发送到位串操作 单位以获得操纵的操纵目标数据。 特殊数据设定单元还从特殊数据设定请求中提取逻辑块地址信息，并指示访问单元将操作操作目标数据中的魔术数字写入用户数据存储区域，并将错误检测码写入被操纵的 将操作对象数据提供给由逻辑块地址信息定位的存储区域中的冗余区域。

    Controller and memory system for managing data
    53.
    发明授权
    Controller and memory system for managing data 失效
    用于管理数据的控制器和存储器系统

    公开(公告)号：US08516182B2

    公开(公告)日：2013-08-20

    申请号：US12554272

    申请日：2009-09-04

    申请人： Kenichiro Yoshii ,  Shinichi Kanno ,  Shigehiro Asano

    发明人： Kenichiro Yoshii ,  Shinichi Kanno ,  Shigehiro Asano

    IPC分类号： G06F12/10

    CPC分类号： G06F12/0246 ,  G06F2212/7207 ,  G06F2212/7209

    摘要： A controller includes a storage for a translation table showing logical and physical addresses in a flash memory in correspondence with one another; another storage storing FAT information indicating the state of data stored in each of pages contained in each of blocks and FAT information identifiers each identifying a block to which pages each storing therein the data in the state indicated by the FAT information belong, while keeping them in correspondence with one another; yet another storage for a block management table showing block identifiers, use-state judging information indicating whether the corresponding block is used/unused, and the FAT information identifiers corresponding to all the blocks indicated as being used by the use-state judging information, while keeping them in correspondence with one another; and a controller controlling unit managing data stored in the flash memory by using the translation table, the FAT information, and the block management table.

    摘要翻译： 控制器包括用于转换表的存储器，其中显示闪存中的逻辑和物理地址彼此对应; 指示存储在每个块中的每个页面中存储的数据的状态的FAT信息和每个识别由FAT信息指示的状态中存储有数据的页面所属的块的FAT信息标识符，同时保持它们 相互对应; 另一个用于表示块标识符的块管理表的存储器，指示是否使用相应块的使用状态判断信息以及与使用状态判断信息所使用的所有块对应的FAT信息标识符，而 保持彼此对应; 以及控制器控制单元，通过使用转换表，FAT信息和块管理表来管理存储在闪速存储器中的数据。

    Semiconductor memory device
    54.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US08418042B2

    公开(公告)日：2013-04-09

    申请号：US12889018

    申请日：2010-09-23

    申请人： Shinichi Kanno

    发明人： Shinichi Kanno

    IPC分类号： H03M13/00

    CPC分类号： G06F11/1068 ,  G06F11/1012 ,  G06F11/1072 ,  G06F11/1076 ,  G11C16/10 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1515 ,  H03M13/29 ,  H03M13/2906

    摘要： A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction. If the number of errors exceeds an erasure correction capability of the RS code, normal error correction using the RS code is performed, and further error correction using the BCH code is performed.

    MEMORY SYSTEM
    55.
    发明申请
    MEMORY SYSTEM 审中-公开
    记忆系统

    公开(公告)号：US20120179942A1

    公开(公告)日：2012-07-12

    申请号：US13426696

    申请日：2012-03-22

    申请人： Yasushi NAGADOMI ,  Daisaburo Takashima ,  Kosuke Hatsuda ,  Shinichi Kanno

    发明人： Yasushi NAGADOMI ,  Daisaburo Takashima ,  Kosuke Hatsuda ,  Shinichi Kanno

    IPC分类号： G06F11/26

    CPC分类号： G11C16/349 ,  G06F11/008 ,  G06F11/1068

    摘要： To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used.The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.

    摘要翻译： 提供一种确定诸如耗尽水平的存储器状态并且允许有效地使用存储器的存储器系统。 存储器系统包括NAND型闪速存储器1，数据可以被电写入/擦除;非易失性存储器2，对NAND型闪速存储器1的擦除操作次数进行计数，并保持擦除次数和最大数量 擦除操作，以及控制器3，其具有从计算机4被给予自诊断命令的连接接口31，并且基于自身检测从非易失性存储器2检索擦除操作的次数和擦除操作的最大次数， 诊断命令，并通过连接接口31输出擦除操作次数和最大擦除次数。

    Semiconductor memory device and method of controlling the same
    56.
    发明授权
    Semiconductor memory device and method of controlling the same 有权
    半导体存储器件及其控制方法

    公开(公告)号：US08196008B2

    公开(公告)日：2012-06-05

    申请号：US13090539

    申请日：2011-04-20

    申请人： Shinichi Kanno ,  Hironori Uchikawa

    发明人： Shinichi Kanno ,  Hironori Uchikawa

    IPC分类号： H03M13/00

    CPC分类号： H03M13/2906 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1068 ,  G06F13/1673 ,  G06F13/4068 ,  G11C29/52 ,  H03M13/03 ,  H03M13/29 ,  H03M13/35 ,  H03M13/6561 ,  Y02D10/14 ,  Y02D10/151

    摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

    摘要翻译： 半导体存储器件包括多个检测码发生器，其被配置为分别产生多个检测码以分别检测多个数据项中的错误;多个第一校正码发生器，被配置为产生多个第一校正码以校正错误 在多个第一数据块中，分别包含数据项之一和相应检测码的第一数据块，被配置为生成用于校正第二数据块中的错误的第二校正码的第二校正码发生器， 包含第一数据块的第二数据块，以及被配置为非易失性地存储第二数据块，第一校正码和第二校正码的半导体存储器。

    Memory controller controlling semiconductor storage device and semiconductor device
    59.
    发明授权
    Memory controller controlling semiconductor storage device and semiconductor device 失效
    存储控制器控制半导体存储器件和半导体器件

    公开(公告)号：US07848143B2

    公开(公告)日：2010-12-07

    申请号：US12687915

    申请日：2010-01-15

    申请人： Shinichi Kanno ,  Yosuke Kuroda ,  Toshio Shirakihara

    发明人： Shinichi Kanno ,  Yosuke Kuroda ,  Toshio Shirakihara

    IPC分类号： G11C16/00

    CPC分类号： G11C16/3418

    摘要： A memory controller controls a semiconductor storage device including nonvolatile memory cells. The controller includes a generating circuit, and a selection circuit. The generating circuit generates first data based on a second data. The selection circuit retains a cumulative value whose each digit is a cumulative result in each bit of data which is already written in the memory cells. The selection circuit selects one of the first data. A selected first data has a better average of digits in a sum of each bit of the selected first data and each digit of the cumulative value than an unselected first data. The selection circuit retains the sum concerning the selected first data as the new cumulative value.

    摘要翻译： 存储器控制器控制包括非易失性存储单元的半导体存储器件。 控制器包括发生电路和选择电路。 生成电路基于第二数据生成第一数据。 选择电路保留累积值，其每个数字是已经写入存储器单元的每个数据位的累积结果。 选择电路选择第一数据之一。 所选择的第一数据在所选择的第一数据的每一比特和累积值的每个数字之和与未选择的第一数据的和中具有更好的数字平均。 选择电路将与所选择的第一数据相关的和保持为新的累积值。

    Processor, control device for a processor, clock frequency determining method and source voltage controlling method of a processor
    60.
    发明授权
    Processor, control device for a processor, clock frequency determining method and source voltage controlling method of a processor 失效
    处理器，处理器的控制装置，处理器的时钟频率确定方法和源电压控制方法

    公开(公告)号：US07644297B2

    公开(公告)日：2010-01-05

    申请号：US11819417

    申请日：2007-06-27

    申请人： Masaya Tarui ,  Shinichi Kanno

    发明人： Masaya Tarui ,  Shinichi Kanno

    IPC分类号： G06F1/04 ,  G06F1/00

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： A processor comprises a clock signal generator generating clock signals; an operational processing part performing data processing which is divided into a plurality of execution units, in accordance with the clock signals; a storage storing data used when each execution unit is executed by the operational processing part; a data amount detector detecting amounts of the data stored in the storage per each execution unit; a clock frequency determining part determining a new clock frequency of the clock signals by using the amounts of the data, said clock signals being supplied newly to the operational processing part.

    摘要翻译： 处理器包括产生时钟信号的时钟信号发生器; 操作处理部分，根据所述时钟信号执行被分成多个执行单元的数据处理; 当由所述操作处理部执行每个执行单元时使用的存储数据的存储器; 数据量检测器，检测每个执行单元存储在存储器中的数据量; 时钟频率确定部分，通过使用所述数据量确定所述时钟信号的新时钟频率，所述时钟信号被新近提供给所述操作处理部分。