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公开(公告)号：US07612404B2
公开(公告)日：2009-11-03
申请号：US11783933
申请日：2007-04-13
申请人： Akihito Yamamoto , Masayuki Tanaka , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujisuka , Katsuaki Natori , Hirokazu Ishida , Yoshio Ozawa
发明人： Akihito Yamamoto , Masayuki Tanaka , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujisuka , Katsuaki Natori , Hirokazu Ishida , Yoshio Ozawa
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L27/115 , H01L27/11521 , H01L29/42336 , H01L29/513
摘要： A semiconductor device includes semiconductor substrate, isolation insulating film, nonvolatile memory cells, each of the cells including tunnel insulating film, FG electrode, CG electrode, interelectrode insulating film between the CG and FG electrodes and including a first insulating film and a second insulating film on the first insulating film and having higher permittivity than the first insulating film, the interelectrode insulating film being provided on a side wall of the floating gate electrode in a cross-section view of a channel width direction of the cell, thickness of the interelectrode insulating film increasing from an upper portion of the side wall toward a lower portion of the side wall, thickness of the second insulating film on an upper corner of the FG electrode being thicker than thickness of the second insulating film on the other portions of the side wall in the cross-section view of the channel width direction.
摘要翻译： 半导体器件包括半导体衬底，隔离绝缘膜，非易失性存储单元，每个单元包括隧道绝缘膜，FG电极，CG电极，CG和FG电极之间的电极间绝缘膜，并且包括第一绝缘膜和第二绝缘膜 在第一绝缘膜上并且具有比第一绝缘膜高的介电常数，电极间绝缘膜设置在浮栅电极的侧壁上，在电池的沟道宽度方向的横截面图中，绝缘电极的绝缘层的厚度 膜从侧壁的上部向侧壁的下部增加，FG电极的上角上的第二绝缘膜的厚度比侧壁的其他部分上的第二绝缘膜的厚度厚 在通道宽度方向的横截面视图中。
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52.发明申请公开(公告)号：US20090233451A1
公开(公告)日：2009-09-17
申请号：US12471830
申请日：2009-05-26
申请人： Yoshitaka Tsunashima , Seiji Ihumiya , Yasumasa Suizu , Yoshio Ozawa , Kiyotaka Miyano , Masayuki Tanaka
发明人： Yoshitaka Tsunashima , Seiji Ihumiya , Yasumasa Suizu , Yoshio Ozawa , Kiyotaka Miyano , Masayuki Tanaka
IPC分类号： H01L21/31
CPC分类号： H01L21/82345 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/31604 , H01L21/823462 , H01L21/823475 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6656
摘要： Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.
摘要翻译： 权利要求和公开的是一种半导体器件，包括具有在包含金属，硅和氧的金属硅酸盐的化合物中含有氮或氟的栅极绝缘膜结构的晶体管，具有非晶态金属氧化物层叠结构的栅极绝缘膜结构 膜和金属硅酸盐膜，或具有包括第一金属元素的氧化物膜的第一栅极绝缘膜和包括第二金属元素的金属硅酸盐膜的第二栅极绝缘膜的栅极绝缘膜结构。
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公开(公告)号：US07372113B2
公开(公告)日：2008-05-13
申请号：US10880508
申请日：2004-07-01
申请人： Masayuki Tanaka , Yoshio Ozawa , Shigehiko Saida , Akira Goda , Mitsuhiro Noguchi , Yuichiro Mitani , Yoshitaka Tsunashima
发明人： Masayuki Tanaka , Yoshio Ozawa , Shigehiko Saida , Akira Goda , Mitsuhiro Noguchi , Yuichiro Mitani , Yoshitaka Tsunashima
IPC分类号： H01L21/314
CPC分类号： H01L21/022 , H01L21/0217 , H01L21/28176 , H01L21/28202 , H01L21/28247 , H01L21/28282 , H01L21/28518 , H01L21/3185 , H01L21/76838 , H01L21/76897 , H01L29/513 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/792
摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.
摘要翻译： 公开了一种半导体器件，包括半导体衬底，栅电极，形成在半导体衬底和栅电极之间的第一绝缘膜，以及沿着栅电极的顶表面或侧表面形成的第二绝缘膜， 包含氮，硅和氢的氮化硅膜和形成在下部氮化硅膜上并含有氮，硅和氢的上部氮化硅膜，并且其中氮（N）与硅（Si）的组成比N / Si在 下氮化硅膜比上述氮化硅膜高。
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公开(公告)号：US07368780B2
公开(公告)日：2008-05-06
申请号：US11763070
申请日：2007-06-14
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/513
摘要： A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate of polysilicon provided on each of the element formation regions through a first insulation film, a second insulation film, provided on the floating gate, containing a metal element, a control gate of polysilicon, provided on the second insulation film, and source/drain regions provided in the semiconductor substrate, both a polysilicon conductive layer containing a metal element and a mutual diffusion layer composed of a silicate layer of a mixed oxide material composed of a silicon element contained in the floating gate and the control gate and a metal element contained in the second insulation film are provided on a surface of each of the floating gate and the control gate, respectively.
摘要翻译： 半导体存储器件包括半导体衬底，隔离绝缘膜，填充在形成于半导体衬底中的多个沟槽中，以限定多个元件形成区域;多晶硅浮置栅极，通过第一绝缘层设置在每个元件形成区域上; 设置在浮置栅极上的第二绝缘膜，包含设置在第二绝缘膜上的金属元件，多晶硅控制栅极和设置在半导体衬底中的源极/漏极区域，包含金属的多晶硅导电层 元件和由浮置栅极中包含的硅元素和控制栅极组成的混合氧化物材料的硅酸盐层和包含在第二绝缘膜中的金属元素构成的互扩散层设置在每个浮动栅极的表面上 门和控制门。
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公开(公告)号：US20080017914A1
公开(公告)日：2008-01-24
申请号：US11822437
申请日：2007-07-05
申请人： Katsuaki Natori , Masayuki Tanaka , Katsuyuki Sekine , Hirokazu Ishida , Masumi Matsuzaki , Yoshio Ozawa
发明人： Katsuaki Natori , Masayuki Tanaka , Katsuyuki Sekine , Hirokazu Ishida , Masumi Matsuzaki , Yoshio Ozawa
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： There is disclosed a semiconductor device including a plurality of memory cell transistors, each memory cell transistor including a floating gate electrode isolated from each other via an isolation insulating film every memory cell transistor, an inter-electrode insulating film comprising a HfxAl1-xOy film (0.8≦x≦0.95) formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film, wherein the memory cell transistors are arrayed to form a memory cell array.
摘要翻译： 公开了一种包括多个存储单元晶体管的半导体器件，每个存储单元晶体管包括通过每个存储单元晶体管的隔离绝缘膜彼此隔离的浮栅，包括Hf x 形成在浮置栅电极上的Al 1-x O O y O y膜（0.8 <= x <= 0.95），以及形成在栅极上的控制栅电极 - 电极绝缘膜，其中存储单元晶体管被排列以形成存储单元阵列。
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公开(公告)号：US20070241388A1
公开(公告)日：2007-10-18
申请号：US11783933
申请日：2007-04-13
申请人： Akihito Yamamoto , Masayuki Tanaka , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujitsuka , Katsuaki Natori , Hirokazu Ishida , Yoshio Ozawa
发明人： Akihito Yamamoto , Masayuki Tanaka , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujitsuka , Katsuaki Natori , Hirokazu Ishida , Yoshio Ozawa
IPC分类号： H01L29/76
CPC分类号： H01L29/7883 , H01L27/115 , H01L27/11521 , H01L29/42336 , H01L29/513
摘要： A semiconductor device includes semiconductor substrate, isolation insulating film, nonvolatile memory cells, each of the cells including tunnel insulating film, FG electrode, CG electrode, interelectrode insulating film between the CG and FG electrodes and including a first insulating film and a second insulating film on the first insulating film and having higher permittivity than the first insulating film, the interelectrode insulating film being provided on a side wall of the floating gate electrode in a cross-section view of a channel width direction of the cell, thickness of the interelectrode insulating film increasing from an upper portion of the side wall toward a lower portion of the side wall, thickness of the second insulating film on an upper corner of the FG electrode being thicker than thickness of the second insulating film on the other portions of the side wall in the cross-section view of the channel width direction.
摘要翻译： 半导体器件包括半导体衬底，隔离绝缘膜，非易失性存储单元，每个单元包括隧道绝缘膜，FG电极，CG电极，CG和FG电极之间的电极间绝缘膜，并且包括第一绝缘膜和第二绝缘膜 在第一绝缘膜上并且具有比第一绝缘膜高的介电常数，电极间绝缘膜设置在浮栅电极的侧壁上，在电池的沟道宽度方向的横截面图中，绝缘电极的绝缘层的厚度 膜从侧壁的上部向侧壁的下部增加，FG电极的上角上的第二绝缘膜的厚度比侧壁的其他部分上的第二绝缘膜的厚度厚 在通道宽度方向的横截面视图中。
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57.发明申请公开(公告)号：US20070183208A1
公开(公告)日：2007-08-09
申请号：US11653278
申请日：2007-01-16
CPC分类号： G11C16/3418 , G11C16/0483 , G11C16/3427 , G11C16/3454
摘要： A plurality of memory cell transistors each of which has a gate structure having a floating gate electrode formed of a first conductive film and stacked on an element region surrounded by an element isolation region on a silicon substrate with a first insulating film disposed therebetween and a control gate electrode formed of a second conductive film and stacked on the first conductive film with a second insulating film with a large dielectric constant disposed therebetween are arranged in a memory cell array. A detrap pulse supply circuit generates and supplies a detrap pulse signal to the control gate electrode of the memory cell transistor to extract charges from the second insulating film after data is written into each of the memory cell transistors.
摘要翻译： 多个存储单元晶体管，每个存储单元晶体管具有栅极结构，该栅极结构具有由第一导电膜形成并浮置在由硅衬底上的元件隔离区域围绕的元件区域上的浮置栅电极，其间设置有第一绝缘膜， 在存储单元阵列中布置由第二导电膜形成的层叠在具有介电常数大的第二绝缘膜的第一导电膜上的栅电极。 去除脉冲电源电路产生并提供去除脉冲信号到存储单元晶体管的控制栅电极，以便在将数据写入每个存储单元晶体管之后从第二绝缘膜提取电荷。
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公开(公告)号：US06927139B2
公开(公告)日：2005-08-09
申请号：US10717719
申请日：2003-11-21
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A semiconductor memory encompasses a memory cell matrix, which embraces device isolation films running along the column-direction, arranged alternatively between the cell columns; first conductive layers having top surfaces lower than the device isolation films; inter-electrode dielectrics arranged on the corresponding first conductive layers, the inter-electrode dielectric has a dielectric constant larger than that of silicon oxide; and second conductive layers running along the row-direction, each of the second conductive layers arranged on the inter-electrode dielectric and the device isolation films so that the second conductive layer can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns.
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公开(公告)号：US08791521B2
公开(公告)日：2014-07-29
申请号：US13423664
申请日：2012-03-19
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： A semiconductor device includes an interelectrode insulating film formed between a charge storage layer and a control electrode layer. The interelectrode insulating film is formed in a first region above an upper surface of an element isolation insulating film, a second region along a sidewall of the charge storage layer, and a third region above an upper surface of the charge storage layer. The interelectrode insulating film includes a first stack including a first silicon nitride film or a high dielectric constant film interposed between a first and a second silicon oxide film or a second stack including a second high dielectric constant film and a third silicon oxide film, and a second silicon nitride film formed between the control electrode layer and the first or the second stack. The second silicon nitride film is relatively thinner in the third region than in the first region.
摘要翻译： 半导体器件包括在电荷存储层和控制电极层之间形成的电极间绝缘膜。 电极间绝缘膜形成在元件隔离绝缘膜的上表面上方的第一区域，沿着电荷存储层的侧壁的第二区域和电荷存储层的上表面上方的第三区域。 电极间绝缘膜包括：第一堆叠，其包括介于第一和第二氧化硅膜之间的第一氮化硅膜或高介电常数膜，或包括第二高介电常数膜和第三氧化硅膜的第二堆叠， 形成在控制电极层和第一或第二堆叠之间的第二氮化硅膜。 在第三区域中，第二氮化硅膜比第一区域相对薄。
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公开(公告)号：US08525252B2
公开(公告)日：2013-09-03
申请号：US13233788
申请日：2011-09-15
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0466 , H01L21/28282 , H01L27/11568 , H01L27/11582 , H01L29/4234 , H01L29/66833 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor region, a tunnel insulator provided above the semiconductor region, a charge storage insulator provided above the tunnel insulator, a block insulator provided above the charge storage insulator, a control gate electrode provided above the block insulator, and an interface region including a metal element, the interface region being provided at one interface selected from between the semiconductor region and the tunnel insulator, the tunnel insulator and the charge storage insulator, the charge storage insulator and the block insulator, and the block insulator and the control gate electrode.
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