公开(公告)号：US08670264B1

公开(公告)日：2014-03-11

申请号：US13585774

申请日：2012-08-14

申请人： Ebrahim Abedifard ,  Parviz Keshtbod

发明人： Ebrahim Abedifard ,  Parviz Keshtbod

IPC分类号： G11C11/21

CPC分类号： G11C11/1673 ,  G11C8/16 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675

摘要： A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.

摘要翻译： 存储器阵列被组织成电阻元件的行和列，并且被公开为包括要读取或要写入的电阻元件。 此外，第一存取晶体管耦合到电阻元件和第一源极线，第二存取晶体管耦合到电阻元件和第二源极线，电阻元件在一端被耦合到第一和第二存取 晶体管和位线的相对端。 存储器阵列还具有各自耦合到位线的其它电阻元件。 在读取其中一个或多个其它电阻元件的同时写入电阻元件。

公开(公告)号：US08644060B2

公开(公告)日：2014-02-04

申请号：US13491159

申请日：2012-06-07

申请人： Ebrahim Abedifard ,  Parviz Keshtbod

发明人： Ebrahim Abedifard ,  Parviz Keshtbod

IPC分类号： G11C11/00

CPC分类号： G11C11/1673 ,  G11C11/1657

摘要： A MTJ is sensed by applying a first reference current, first programming the MTJ to a first value using the first reference current, detecting the resistance of the first programmed MTJ, and if the detected resistance is above a first reference resistance, declaring the MTJ to be at a first state. Otherwise, upon determining if the detected resistance is below a second reference resistance, declaring the MTJ to be at a second state. In some cases, applying a second reference current through the MTJ and second programming the MTJ to a second value using the second reference current. Detecting the resistance of the second programmed MTJ and in some cases, declaring the MTJ to be at the second state, and in other cases, declaring the MTJ to be at the first state and programming the MTJ to the second state.

摘要翻译： 通过施加第一参考电流来感测MTJ，首先使用第一参考电流将MTJ编程为第一值，检测第一编程MTJ的电阻，并且如果检测到的电阻高于第一参考电阻，则将MTJ声明为 处于第一个状态。 否则，在确定检测到的电阻是否低于第二参考电阻时，声明MTJ处于第二状态。 在某些情况下，通过MTJ施加第二参考电流，并使用第二参考电流对MTJ进行第二次编程。 检测第二个编程的MTJ的电阻，并且在某些情况下，声明MTJ处于第二状态，在其他情况下，声明MTJ处于第一状态并将MTJ编程到第二状态。

公开(公告)号：US20120275219A1

公开(公告)日：2012-11-01

申请号：US13546408

申请日：2012-07-11

申请人： Ebrahim Abedifard

发明人： Ebrahim Abedifard

IPC分类号： G11C11/16

CPC分类号： G11C8/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C2213/75

摘要： A spin-torque transfer memory random access memory (STTMRAM) cell is disclosed comprising a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ.

摘要翻译： 公开了一种自旋转矩传递存储器随机存取存储器（STTMRAM）单元，其包括被识别为被编程的所选择的磁性隧道结（MTJ）; 具有第一端口，第二端口和栅极的第一晶体管，耦合到所选择的MTJ的第一晶体管的第一端口; 通过第一晶体管的第二端口耦合到所选择的MTJ的第一相邻MTJ; 具有第一端口，第二端口和栅极的第二晶体管，耦合到所选择的MTJ的第二晶体管的第一端口; 通过第二晶体管的第二端口耦合到所选择的MTJ的第二相邻MTJ; 耦合到所选MTJ的第二端的第一位/源极线; 以及耦合到第一相邻MTJ的第二端和第二相邻MTJ的第二端的第二位/源极线。

公开(公告)号：US20110149660A1

公开(公告)日：2011-06-23

申请号：US13030701

申请日：2011-02-18

申请人： Uday Chandrasekhar ,  Ebrahim Abedifard ,  Allahyar Vahidimowlavi

发明人： Uday Chandrasekhar ,  Ebrahim Abedifard ,  Allahyar Vahidimowlavi

IPC分类号： G11C16/26

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/32 ,  G11C2211/5621

摘要： Methods for sensing in a memory device and a memory device are disclosed. In one such sensing method, a single read operation with multiple sense amplifier circuit comparisons to a reference threshold level are performed to determine a state of a selected memory cell. A ramped voltage turns on the selected memory cell when the ramped voltage reaches the threshold voltage to which the selected memory cell is programmed. In one embodiment, the turned on memory cell discharges its respective bit line.

摘要翻译： 公开了一种在存储器件和存储器件中进行感测的方法。 在一种这样的感测方法中，执行具有多个读出放大器电路与参考阈值电平比较的单次读取操作，以确定所选择的存储器单元的状态。 当斜坡电压达到编程所选存储单元的阈值电压时，斜坡电压打开所选存储单元。 在一个实施例中，导通的存储器单元放电其相应的位线。

公开(公告)号：US07952924B2

公开(公告)日：2011-05-31

申请号：US12827892

申请日：2010-06-30

申请人： Frankie F. Roohparvar ,  Ebrahim Abedifard

发明人： Frankie F. Roohparvar ,  Ebrahim Abedifard

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/12 ,  G11C16/3459 ,  G11C2216/14

摘要： A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines of an array row are concurrently programmed as a common page. Floating gate coupling during programming can therefore be reduced. Multiple verify operations are performed on separate bit lines of the page. Bit line coupling can therefore be reduced.

摘要翻译： 描述了一种NAND闪存器件，其可以在编程和验证操作期间减少位线耦合和浮动栅极耦合。 阵列行的连续位线被同时编程为公共页面。 因此可以减少编程期间的浮动栅极耦合。 在页面的单独位线上执行多个验证操作。 因此可以减少位线耦合。

公开(公告)号：US20080266924A1

公开(公告)日：2008-10-30

申请号：US11739717

申请日：2007-04-25

申请人： Ebrahim Abedifard

发明人： Ebrahim Abedifard

IPC分类号： G11C5/02 ,  G11C16/04

CPC分类号： G11C8/04 ,  G11C16/08 ,  G11C2216/30

摘要： A NAND interface having a reduced pin count configuration, in which all command and address functions and operations of the NAND are provided serially on a single serial command and address pin.

摘要翻译： 具有减少的引脚计数配置的NAND接口，其中所有命令和地址功能和NAND的操作在单个串行命令和地址引脚上串行提供。

公开(公告)号：US20070263449A1

公开(公告)日：2007-11-15

申请号：US11433562

申请日：2006-05-15

申请人： Erwin Yu ,  Ebrahim Abedifard ,  Frederick Jaffin ,  Uday Chandrasekhar

发明人： Erwin Yu ,  Ebrahim Abedifard ,  Frederick Jaffin ,  Uday Chandrasekhar

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C16/12 ,  G11C16/04 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array using a minimum number of programming pulses.

摘要翻译： 一种提供在闪速存储器件中控制具有不同宽度和/或电压的编程脉冲的能力的方法和装置。 设置编程脉冲的宽度和/或电压电平以使用最少数量的编程脉冲对阵列的所有存储单元进行编程。

公开(公告)号：US07269083B2

公开(公告)日：2007-09-11

申请号：US11473466

申请日：2006-06-23

申请人： Ebrahim Abedifard

发明人： Ebrahim Abedifard

IPC分类号： G11C29/00

CPC分类号： G11C29/846 ,  G11C8/12 ,  G11C16/0483 ,  G11C29/789

摘要： An access request for a first memory location of a memory device is received at the memory device. A second memory location is selected in response to the request without regard to an address signal.

摘要翻译： 在存储器设备处接收对存储器设备的第一存储器位置的访问请求。 响应于该请求选择第二存储器位置而不考虑地址信号。

公开(公告)号：US07248499B2

公开(公告)日：2007-07-24

申请号：US11480127

申请日：2006-06-30

申请人： Chang Wan Ha ,  Ebrahim Abedifard

发明人： Chang Wan Ha ,  Ebrahim Abedifard

IPC分类号： G11C5/06 ,  G11C11/34 ,  G11C16/08

CPC分类号： G11C5/025 ,  G11C16/0483 ,  G11C16/08

摘要： A memory array including a first region in which a first memory sub-array is located and a second region separated from the first region in which a second memory sub-array is located. The first and second memory sub-arrays have flash memory cells coupled to a plurality of word lines. A driver region separates the first and second regions and includes word line driver circuits coupled to the word lines of the first and second memory sub-arrays. A row decoder region adjacent the first region and separate from the driver region includes at least some sub-circuits of row decoder circuits located therein. The row decoder circuits are coupled to the word line driver circuits located in the driver region and are configured to activate driver circuits to drive word lines of the first and second memory sub-arrays in response to decoding address signals selecting the particular row decoder circuit.

摘要翻译： 一种存储器阵列，包括第一存储器子阵列所在的第一区域和与第二存储器子阵列所在的第一区域分离的第二区域。 第一和第二存储器子阵列具有耦合到多个字线的闪存单元。 驱动器区域分离第一和第二区域，并且包括耦合到第一和第二存储器子阵列的字线的字线驱动电路。 与第一区域相邻并且与驱动器区域分开的行解码器区域包括位于其中的行解码器电路的至少一些子电路。 行解码器电路耦合到位于驱动器区域中的字线驱动器电路，并且被配置为响应于选择特定行解码器电路的解码地址信号而激活驱动电路以驱动第一和第二存储器子阵列的字线。

公开(公告)号：US20060239091A1

公开(公告)日：2006-10-26

申请号：US11473466

申请日：2006-06-23

申请人： Ebrahim Abedifard

发明人： Ebrahim Abedifard

IPC分类号： G11C29/00

CPC分类号： G11C29/846 ,  G11C8/12 ,  G11C16/0483 ,  G11C29/789

摘要： An access request for a first memory location of a memory device is received at the memory device. A second memory location is selected in response to the request without regard to an address signal.

摘要翻译： 在存储器设备处接收对存储器设备的第一存储器位置的访问请求。 响应于该请求选择第二存储器位置而不考虑地址信号。