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公开(公告)号：US07985984B2
公开(公告)日：2011-07-26
申请号：US12528578
申请日：2008-02-26
IPC分类号： H01L29/778
CPC分类号： H01L29/42316 , H01L29/2003 , H01L29/7781
摘要： Provided is a semiconductor device that can reduce the contact resistance, has a small current collapse, and can improve the pinch-off characteristic upon a high-frequency operation. A field effect transistor using a wurtzite (having (0001) as the main plane) type III-nitride semiconductor includes: a substrate (101); an undercoat layer (103) of a first III-nitride semiconductor; and a carrier travel layer (104) of a second III-nitride semiconductor. The undercoat layer (103) (101) and the carrier travel layer (104) is formed on the substrate in this order. The field effect transistor includes source/drain electrodes (105, 106) in ohmic contact, and a gate electrode (107) in Schottky contact directly or via another layer on the carrier travel layer (104). The undercoat layer (103) has an average lattice constant greater than that of the carrier travel layer (104) and a band gap greater than that of the carrier travel layer (104).
摘要翻译： 提供了能够降低接触电阻，具有小的电流崩溃的半导体器件，并且可以在高频操作时提高夹断特性。 使用纤锌矿（具有（0001）作为主面）的III型氮化物半导体的场效应晶体管包括：衬底（101）; 第一III族氮化物半导体的底涂层（103） 和第二III族氮化物半导体的载流子行进层（104）。 底涂层（103）（101）和载体移动层（104）依次形成在基板上。 场效应晶体管包括欧姆接触的源极/漏极（105,106）和直接或通过载流子行进层（104）上的另一层的肖特基接触的栅电极（107）。 底涂层（103）的平均晶格常数大于载体移动层（104）的平均晶格常数，并且带隙大于载流子行进层（104）的平均晶格常数。
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公开(公告)号：US07859014B2
公开(公告)日：2010-12-28
申请号：US11571290
申请日：2005-06-24
申请人： Tatsuo Nakayama , Hironobu Miyamoto , Yuji Ando , Masaaki Kuzuhara , Yasuhiro Okamoto , Takashi Inoue , Koji Hataya
发明人： Tatsuo Nakayama , Hironobu Miyamoto , Yuji Ando , Masaaki Kuzuhara , Yasuhiro Okamoto , Takashi Inoue , Koji Hataya
IPC分类号： H01L29/66
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/4236 , H01L29/42376 , H01L29/78
摘要： The present invention provides a semiconductor device capable of suppressing current collapse, and also of preventing dielectric breakdown voltage and gain from lowering so as to perform high-voltage operation and realize an ideal high output. On a substrate (101), there are formed a buffer layer (102) made of a first GaN-based semiconductor, a carrier traveling layer (103) made of a second GaN-based semiconductor and a carrier supplying layer (104) made of a third GaN-based semiconductor. A recess structure (108) is made by eliminating a part of a first insulation film (107) and a part of the carrier supplying layer (104). Next, a gate insulation film (109) is deposited, and then a gate electrode (110) is formed so as to fill up the recess portion (108) and cover on over an area where the first insulation film (107) remains so that its portion on the drain electrode side is longer than that on the source electrode side. Such a recess structure is employed so as to provide the high-output semiconductor device capable of performing the high-voltage operation.
摘要翻译： 本发明提供一种能够抑制电流塌陷以及防止电介质击穿电压和增益降低的半导体器件，从而进行高压操作并实现理想的高输出。 在基板（101）上形成有由第一GaN基半导体构成的缓冲层（102），由第二GaN基半导体构成的载流子移动层（103）和由 第三GaN基半导体。 通过消除第一绝缘膜（107）的一部分和载体供给层（104）的一部分来制造凹陷结构（108）。 接下来，沉积栅极绝缘膜（109），然后形成栅极电极（110），以填充凹部（108）并覆盖在第一绝缘膜（107）保留的区域上，使得 其漏电极侧的部分比源电极侧的部分长。 采用这样的凹部结构来提供能够执行高电压操作的高输出半导体器件。
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公开(公告)号：US07459788B2
公开(公告)日：2008-12-02
申请号：US10590730
申请日：2005-02-28
申请人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Masaaki Kuzuhara , Yasuhiro Okamoto , Takashi Inoue , Koji Hataya
发明人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Masaaki Kuzuhara , Yasuhiro Okamoto , Takashi Inoue , Koji Hataya
摘要： An ohmic electrode structure of a nitride semiconductor device having a nitride semiconductor. The ohmic electrode structure is provided with a first metal film formed on the nitride semiconductor and a second metal film formed on the first metal film. The first metal film is composed of at least one material selected from a group consisting of V, Mo, Ti, Nb, W, Fe, Hf, Re, Ta and Zr. The second metal film is composed of at least one material different from that of the first metal film (102), selected from a group consisting of V, Mo, Ti, Nb, W, Fe, Hf, Re, Ta, Zr, Pt and Au.
摘要翻译： 具有氮化物半导体的氮化物半导体器件的欧姆电极结构。 欧姆电极结构设置有形成在氮化物半导体上的第一金属膜和形成在第一金属膜上的第二金属膜。 第一金属膜由选自V，Mo，Ti，Nb，W，Fe，Hf，Re，Ta和Zr中的至少一种材料构成。 第二金属膜由与V，Mo，Ti，Nb，W，Fe，Hf，Re，Ta，Zr，Pt等组成的组中的至少一种不同于第一金属膜的材料构成 和Au。
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公开(公告)号：US20070158692A1
公开(公告)日：2007-07-12
申请号：US11571290
申请日：2005-06-24
申请人： Tatsuo Nakayama , Hironobu Miyamoto , Yuji Ando , Masaaki Kuzuhara , Yasuhiro Okamoto , Takashi Inoue , Koji Hataya
发明人： Tatsuo Nakayama , Hironobu Miyamoto , Yuji Ando , Masaaki Kuzuhara , Yasuhiro Okamoto , Takashi Inoue , Koji Hataya
IPC分类号： H01L29/76
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/4236 , H01L29/42376 , H01L29/78
摘要： The present invention provides a semiconductor device capable of suppressing current collapse, and also of preventing dielectric breakdown voltage and gain from lowering so as to perform high-voltage operation and realize an ideal high output. On a substrate (101), there are formed a buffer layer (102) made of a first GaN-based semiconductor, a carrier traveling layer (103) made of a second GaN-based semiconductor and a carrier supplying layer (104) made of a third GaN-based semiconductor. A recess structure (108) is made by eliminating a part of a first insulation film (107) and a part of the carrier supplying layer (104). Next, a gate insulation film (109) is deposited, and then a gate electrode (110) is formed so as to fill up the recess portion (108) and cover on over an area where the first insulation film (107) remains so that its portion on the drain electrode side is longer than that on the source electrode side. Such a recess structure is employed so as to provide the high-output semiconductor device capable of performing the high-voltage operation.
摘要翻译： 本发明提供一种能够抑制电流塌陷以及防止电介质击穿电压和增益降低的半导体器件，从而进行高压操作并实现理想的高输出。 在基板（101）上形成有由第一GaN基半导体构成的缓冲层（102），由第二GaN基半导体构成的载流子移动层（103）和由 第三GaN基半导体。 通过消除第一绝缘膜（107）的一部分和载体供给层（104）的一部分来制造凹陷结构（108）。 接下来，沉积栅极绝缘膜（109），然后形成栅电极（110），以填充凹部（108）并覆盖在第一绝缘膜（107）保留的区域上，使得 其漏电极侧的部分比源电极侧的部分长。 采用这样的凹部结构来提供能够执行高电压操作的高输出半导体器件。
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公开(公告)号：US20100155779A1
公开(公告)日：2010-06-24
申请号：US11992755
申请日：2006-09-28
IPC分类号： H01L29/78
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/405 , H01L29/66462
摘要： In a field effect transistor, a Group III nitride semiconductor layer structure containing a hetero junction, a source electrode 101 and a drain electrode 103 formed apart from each other over the Group III nitride semiconductor layer structure, and a gate electrode 102 disposed between these electrodes, are provided. Over the surface of the Group III nitride semiconductor layer structure, a SiO2 film 122 containing oxygen as a constitutive element is provided, in contact with both side faces of the gate electrode 102. Over the surface of the Group III nitride semiconductor layer structure, a SiN film 121 is provided so as to cover the region between the SiO2 film 122 and the source electrode 101, and the region between the SiO2 film 122 and the drain electrode 103. The SiN film 121 is composed of a material different from that composing the SiO2 film 122, and contains nitrogen as a constitutive element.
摘要翻译： 在场效应晶体管中，包含异质结的III族氮化物半导体层结构，在III族氮化物半导体层结构上彼此分开形成的源电极101和漏极103以及设置在这些电极之间的栅极102 ，提供。 在III族氮化物半导体层结构的表面上，提供含有氧作为构成元素的SiO 2膜122，与栅电极102的两个侧面接触。在III族氮化物半导体层结构的表面上， SiN膜121被设置为覆盖SiO 2膜122和源电极101之间的区域以及SiO 2膜122和漏电极103之间的区域。SiN膜121由与不同于构成 SiO 2膜122，并且含有氮作为构成元素。
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公开(公告)号：US20070164326A1
公开(公告)日：2007-07-19
申请号：US10588775
申请日：2005-02-21
申请人： Yasuhiro Okamoto , Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Takashi Inque , Masaaki Kuzuhara
发明人： Yasuhiro Okamoto , Yuji Ando , Hironobu Miyamoto , Tatsuo Nakayama , Takashi Inque , Masaaki Kuzuhara
IPC分类号： H01L29/76
CPC分类号： H01L29/402 , H01L29/2003 , H01L29/42316 , H01L29/7787
摘要： A field effect transistor includes a semiconductor layer structure including GaN channel layer 12 and AlGa electron supply layer 13, source electrode 1 and drain electrode 3 which are formed on electron supply layer 13 so as to be separated from each other, gate electrode 2 formed between source electrode 1 and drain electrode 3, and SiON film 23 formed on electron supply layer 13. Gate electrode 2 has a field plate portion 5 that projects toward drain electrode 3 in the form of an eave on SiON film 23. The thickness of a portion (field plate layer 23a) of SiON film 23 lying between field plate portion 5 and electron supply layer 13 gradually increases from gate electrode 2 to drain electrode 3.
摘要翻译： 场效应晶体管包括：半导体层结构，包括形成在电子供给层13上的GaN沟道层12和AlGa电子供给层13，源电极1和漏电极3，栅电极2形成在 源电极1和漏电极3以及形成在电子供给层13上的SiON膜23。 栅电极2具有在SiON膜23上以檐形式向漏电极3突出的场板部5。 位于场板部5与电子供给层13之间的SiON膜23的一部分（场板层23a）的厚度从栅电极2逐渐增加到漏电极3。
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公开(公告)号：US20050151255A1
公开(公告)日：2005-07-14
申请号：US10518602
申请日：2003-06-17
申请人： Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Kensuke Kasahara , Tatsuo Nakayama , Masaaki Kuzuhara
发明人： Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Kensuke Kasahara , Tatsuo Nakayama , Masaaki Kuzuhara
IPC分类号： H01L29/872 , H01L21/338 , H01L29/20 , H01L29/423 , H01L29/47 , H01L29/778 , H01L29/812 , H01L31/0328
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/475 , H01L29/7781 , H01L29/812
摘要： A GaN semiconductor device with improved heat resistance of the Schottky junction electrode and excellent power performance and reliability is provided. In this semiconductor device having a Schottky gate electrode 17 which is in contact with an AlGaN electron supplying layer 14, a gate electrode 17 comprises a laminated structure wherein a first metal layer 171 formed of any of Ni, Pt and Pd, a second metal layer 172 formed of any of Mo, Pt, W, Ti, Ta, MoSi, PtSi, WSi, TiSi, TaSi, MoN, WN, TiN and TaN, and a third metal layer formed of any of Au, Cu, Al and Pt. Since the second metal layer comprises a metal material having a high melting point, it works as a barrier to the interdiffusion between the first metal layer and the third metal layer, and the deterioration of the gate characteristics caused by high temperature operation is suppressed. Since the first metal layer contacting the AlGaN electron supplying layer 14 has a high work function, the Schottky barrier is high, and superior Schottky contact is obtained.
摘要翻译： 提供了具有肖特基接合电极的耐热性改善并且具有优异的功率性能和可靠性的GaN半导体器件。 在具有与AlGaN电子供给层14接触的肖特基栅电极17的该半导体器件中，栅电极17包括层叠结构，其中由Ni，Pt和Pd中的任一种形成的第一金属层171，第二金属层 由Mo，Pt，W，Ti，Ta，MoSi，PtSi，WSi，TiSi，TaSi，MoN，WN，TiN和TaN中的任一种形成的第一金属层，以及由Au，Cu，Al和Pt中的任一种形成的第三金属层。 由于第二金属层包括具有高熔点的金属材料，所以它作为第一金属层和第三金属层之间的相互扩散的障碍，并且抑制了由高温操作引起的栅极特性的劣化。 由于与AlGaN电子供给层14接触的第一金属层具有高功函数，所以肖特基势垒高，得到优异的肖特基接触。
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公开(公告)号：US07071526B2
公开(公告)日：2006-07-04
申请号：US10518602
申请日：2003-06-17
申请人： Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Kensuke Kasahara , Tatsuo Nakayama , Masaaki Kuzuhara
发明人： Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Kensuke Kasahara , Tatsuo Nakayama , Masaaki Kuzuhara
IPC分类号： H01L27/095 , H01L29/47
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/475 , H01L29/7781 , H01L29/812
摘要： A GaN semiconductor device with improved heat resistance of the Schottky junction electrode and excellent power performance and reliability is provided. In this semiconductor device having a Schottky gate electrode 17 which is in contact with an AlGaN electron supplying layer 14, a gate electrode 17 comprises a laminated structure wherein a first metal layer 171 formed of any of Ni, Pt and Pd, a second metal layer 172 formed of any of Mo, Pt, W, Ti, Ta, MoSi, PtSi, WSi, TiSi, TaSi, MoN, WN, TiN and TaN, and a third metal layer formed of any of Au, Cu, Al and Pt. Since the second metal layer comprises a metal material having a high melting point, it works as a barrier to the interdiffusion between the first metal layer and the third metal layer, and the deterioration of the gate characteristics caused by high temperature operation is suppressed. Since the first metal layer contacting the AlGaN electron supplying layer 14 has a high work function, the Schottky barrier is high, and superior Schottky contact is obtained.
摘要翻译： 提供了具有肖特基接合电极的耐热性改善并且具有优异的功率性能和可靠性的GaN半导体器件。 在具有与AlGaN电子供给层14接触的肖特基栅电极17的该半导体器件中，栅电极17包括层叠结构，其中由Ni，Pt和Pd中的任一种形成的第一金属层171，第二金属层 由Mo，Pt，W，Ti，Ta，MoSi，PtSi，WSi，TiSi，TaSi，MoN，WN，TiN和TaN中的任一种形成的第一金属层，以及由Au，Cu，Al和Pt中的任一种形成的第三金属层。 由于第二金属层包括具有高熔点的金属材料，所以它作为第一金属层和第三金属层之间的相互扩散的障碍，并且抑制了由高温操作引起的栅极特性的劣化。 由于与AlGaN电子供给层14接触的第一金属层具有高功函数，所以肖特基势垒高，得到优异的肖特基接触。
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公开(公告)号：US20060054929A1
公开(公告)日：2006-03-16
申请号：US10515886
申请日：2004-11-29
申请人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Kensuke Kasahara , Yasuhiro Okamoto , Masaaki Kuzuhara
发明人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Kensuke Kasahara , Yasuhiro Okamoto , Masaaki Kuzuhara
IPC分类号： H01L31/109
CPC分类号： H01L29/7783 , H01L29/2003
摘要： A semiconductor device includes, on a substrate (101), a buffer layer (102), and an channel layer (104), consisting essentially of semiconductor of a wultzite compound of group III-V, having a (0001) plane as a principal plane. The channel layer is subjected to compressive strain. A carrier supplying layer (103) is interposed between the channel layer (104) and the buffer layer (102). The carrier supplying layer (103) consists essentially of semiconductor of a wultzite compound of group III-V as a main component. N-type impurities are doped into the entire or part of the carrier supplying layer (103).
摘要翻译： 半导体器件在衬底（101）上包括缓冲层（102）和沟道层（104），该沟道层（104）主要由具有（0001）面作为主体的III-V族的无丝绒化合物的半导体组成 飞机 通道层经受压应变。 载体供给层（103）插入在沟道层（104）和缓冲层（102）之间。 载体供给层（103）主要由作为主要成分的III-V族的无水锰矿化合物的半导体构成。 N型杂质被掺杂到载体供给层（103）的整个或部分中。
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公开(公告)号：US20130069071A1
公开(公告)日：2013-03-21
申请号：US13553759
申请日：2012-07-19
IPC分类号： H01L29/778 , H01L29/205
CPC分类号： H01L29/778 , H01L21/02458 , H01L21/0254 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/432 , H01L29/517 , H01L29/66431 , H01L29/66462 , H01L29/7783
摘要： Compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer. Therefore, negative charge is higher than positive charge at the interface between the cap layer and the barrier layer and the interface between the channel layer and the buffer layer, while positive charge is higher than negative charge at the interface between the barrier layer and the channel. The channel layer has a stacked layer structure of a first layer, a second layer, and a third layer. The second layer has a higher electron affinity than those of the first layer and the third layer.
摘要翻译： 在帽层和阻挡层之间的界面处产生压缩应变，并且在沟道层和缓冲层之间的界面处产生压缩应变，并且在阻挡层和沟道层之间的界面处产生拉伸应变。 因此，负电荷高于帽层和阻挡层之间的界面处的正电荷以及沟道层与缓冲层之间的界面，而正电荷高于阻挡层和沟道之间的界面处的负电荷 。 沟道层具有第一层，第二层和第三层的堆叠层结构。 第二层比第一层和第三层具有更高的电子亲和力。
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